On Tue, Oct 27, 2015 at 02:26:33PM +0100, Maarten Lankhorst wrote: > Now that pixel clock is set to 0 when there are no active pipes it's > easy to set the bypass frequency for this case. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index e9a94ddcba73..ddac097cd08a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5925,7 +5925,6 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, > /* > * FIXME: > * - remove the guardband, it's not needed on BXT > - * - set 19.2MHz bypass frequency if there are no active pipes > */ > if (max_pixclk > 576000*9/10) > return 624000; > @@ -5935,8 +5934,10 @@ static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, > return 384000; > else if (max_pixclk > 144000*9/10) > return 288000; > - else > + else if (max_pixclk) > return 144000; > + else > + return 19200; I think we want to test this on actual hardware before putting it in. Also we might want to do something similar on other platforms too. > } > > /* Compute the max pixel clock for new configuration. Uses atomic state if > -- > 2.1.0 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
