On Wed, Oct 14, 2015 at 07:28:54PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> In preparation for handling more than X tiling, pass the fb modifier to
> gen4_compute_page_offset() instead of the obj->tiling_mode.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/intel_drv.h | 4 ++--
> drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
> 3 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c28fb6a..6add8d1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2447,11 +2447,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
> * is assumed to be a power-of-two. */
> unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
> int *x, int *y,
> - unsigned int tiling_mode,
> + uint64_t fb_modifier,
> unsigned int cpp,
> unsigned int pitch)
> {
> - if (tiling_mode != I915_TILING_NONE) {
> + if (fb_modifier != DRM_FORMAT_MOD_NONE) {
> unsigned int tile_rows, tiles;
>
> tile_rows = *y / 8;
> @@ -2754,7 +2754,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> if (INTEL_INFO(dev)->gen >= 4) {
> intel_crtc->dspaddr_offset =
> intel_gen4_compute_page_offset(dev_priv,
> - &x, &y, obj->tiling_mode,
> + &x, &y, fb->modifier[0],
> pixel_size,
> fb->pitches[0]);
> linear_offset -= intel_crtc->dspaddr_offset;
> @@ -2859,7 +2859,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> linear_offset = y * fb->pitches[0] + x * pixel_size;
> intel_crtc->dspaddr_offset =
> intel_gen4_compute_page_offset(dev_priv,
> - &x, &y, obj->tiling_mode,
> + &x, &y, fb->modifier[0],
> pixel_size,
> fb->pitches[0]);
> linear_offset -= intel_crtc->dspaddr_offset;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 0598932..1152566 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1138,8 +1138,8 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
> int *x, int *y,
> - unsigned int tiling_mode,
> - unsigned int bpp,
> + uint64_t fb_modifier,
> + unsigned int cpp,
> unsigned int pitch);
> void intel_prepare_reset(struct drm_device *dev);
> void intel_finish_reset(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index b229c67..90e27c8 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -422,7 +422,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
> linear_offset = y * fb->pitches[0] + x * pixel_size;
> sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
> &x, &y,
> - obj->tiling_mode,
> + fb->modifier[0],
> pixel_size,
> fb->pitches[0]);
> linear_offset -= sprsurf_offset;
> @@ -556,7 +556,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> linear_offset = y * fb->pitches[0] + x * pixel_size;
> sprsurf_offset =
> intel_gen4_compute_page_offset(dev_priv,
> - &x, &y, obj->tiling_mode,
> + &x, &y, fb->modifier[0],
> pixel_size, fb->pitches[0]);
> linear_offset -= sprsurf_offset;
>
> @@ -694,7 +694,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> linear_offset = y * fb->pitches[0] + x * pixel_size;
> dvssurf_offset =
> intel_gen4_compute_page_offset(dev_priv,
> - &x, &y, obj->tiling_mode,
> + &x, &y, fb->modifier[0],
> pixel_size, fb->pitches[0]);
> linear_offset -= dvssurf_offset;
>
> --
> 2.4.9
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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