On Mon, Oct 19, 2015 at 11:44:12AM +0200, Daniel Vetter wrote: > On Fri, Oct 16, 2015 at 01:23:41PM +0100, Michel Thierry wrote: > > On 10/1/2015 2:16 PM, Daniel Vetter wrote: > > >On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote: > > >>Use 48b addresses if hw supports it (i915.enable_ppgtt=3). > > >>Update the sanitize_enable_ppgtt for 48 bit PPGTT mode. > > >> > > >>Note, aliasing PPGTT remains 32b only. > > >> > > >>v2: s/full_64b/full_48b/. (Akash) > > >>v3: Add sanitize_enable_ppgtt changes until here. (Akash) > > >>v4: Update param description (Chris) > > >> > > >>Cc: Akash Goel <akash.goel@xxxxxxxxx> > > >>Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > >>Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx> > > > > > >Queued for -next, thanks for the patch. Can you please ping someone from > > >mesa to push the libdrm/mesa patches too? > > > > > >Cheers, Daniel > > > > > > > Sorry I didn't report this earlier, but I just realized I can't find this > > patch in the tree. > > Indeed I seem to have never pushed it. Sorry. > > > There's still the discussion of where to apply the 32-bit workaround and the > > different behavior seen in mesa (not if it isn't needed)... but the code was > > written to not require that flag in order to start using the 4-level page > > translation. > > Queued for -next, thanks for the patch. We never got an answer whether there was any impact on existing userspace which is constained to 4GiB (where the last level of pagetables are superfluous). -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
