This patch set enables PASID support for the Intel IOMMU, along with
page request support.
Like its AMD counterpart, it exposes an IOMMU-specific API. I believe
we'll have a session at the Kernel Summit later this month in which we
can work out a generic API which will cover the two (now) existing
implementations as well as upcoming ARM (and other?) versions.
For the time being, however, exposing an Intel-specific API is good
enough, especially as we don't have the required TLP prefix support on
our PCIe root ports and we *can't* support discrete PCIe devices with
PASID support. It's purely on-chip stuff right now, which is basically
only Intel graphics.
The AMD implementation allows a per-device PASID space, and managing
the PASID space is left entirely to the device driver. In contrast,
this implementation maintains a per-IOMMU PASID space, and drivers
calling intel_svm_bind_mm() will be *given* the PASID that they are to
use. In general we seem to be converging on using a single PASID space
across *all* IOMMUs in the system, and this will support that mode of
operation.
The other main different to note is the lifetime management of the
linked mm. This implementation keeps a refcount on the mm and will only
release it when the device driver unbinds the PASID. The AMD
implementation doesn't, and relies on mmu_notifier_release().
v2: Various cleanups
Support multiple devices per PASID
Support deferred invalidation
Add callback to device driver on fault
Fix fault response codes (swap INVALID vs. FAILURE)
Fix PASID/PRI capability handling
--
David Woodhouse Open Source Technology Centre
David.Woodhouse@xxxxxxxxx Intel Corporation
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