Re: [PATCH 22/22] drm/i915: BDW: Pipe level CSC correction

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Regards
Shashank

On 10/13/2015 7:15 PM, Emil Velikov wrote:
On 10 October 2015 at 06:34, Sharma, Shashank <shashank.sharma@xxxxxxxxx> wrote:
On 10/10/2015 5:24 AM, Emil Velikov wrote:

Hi Shashank,

On 9 October 2015 at 20:29, Shashank Sharma <shashank.sharma@xxxxxxxxx>
wrote:

BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.

This patch does the following:
1. Adds the core function to program CSC correction values for
     BDW/SKL/BXT platform
2. Adds CSC correction macros/defines

Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxxxx>
Signed-off-by: Kausal Malladi <kausalmalladi@xxxxxxxxx>
Signed-off-by: Kumar, Kiran S <kiran.s.kumar@xxxxxxxxx>
---
   drivers/gpu/drm/i915/i915_reg.h            |   7 ++
   drivers/gpu/drm/i915/intel_color_manager.c | 114
++++++++++++++++++++++++++++-
   drivers/gpu/drm/i915/intel_color_manager.h |  12 ++-
   3 files changed, 129 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index ed50f75..0e9d252 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8085,4 +8085,11 @@ enum skl_disp_power_wells {
          (_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B,
PAL_PREC_GCMAX_C))


+/* BDW CSC correction */
+#define CSC_COEFF_A                            0x49010
+#define CSC_COEFF_B                            0x49110
+#define CSC_COEFF_C                            0x49210
+#define _PIPE_CSC_COEFF(pipe) \
+       (_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))
+
   #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c
b/drivers/gpu/drm/i915/intel_color_manager.c
index e659382..0a6c00c 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -330,11 +330,119 @@ static int bdw_set_degamma(struct drm_device *dev,
          return 0;
   }

-static s16 chv_prepare_csc_coeff(s64 csc_value)

As mentioned previously, this should be part of the respective patch.

Agree. Looks like diff is messing up a bit. Will take care of this.

+static uint32_t bdw_prepare_csc_coeff(int64_t coeff)
+{
+       uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;
+       int32_t mantissa;
+       uint64_t abs_coeff;
+
+       coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);
+       coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);
+
+       abs_coeff = abs(coeff);
+       if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {
+               /* abs_coeff < 0.125 */
+               exponent_bits = 3;
+               ls_bit_pos = 19;
+       } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&
+               abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {
+               /* abs_coeff >= 0.125 && val < 0.25 */
+               exponent_bits = 2;
+               ls_bit_pos = 20;
+       } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)
+               && abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {
+               /* abs_coeff >= 0.25 && val < 0.5 */
+               exponent_bits = 1;
+               ls_bit_pos = 21;
+       } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)
+               && abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {
+               /* abs_coeff >= 0.5 && val < 1.0 */
+               exponent_bits = 0;
+               ls_bit_pos = 22;
+       } else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&
+               abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {
+               /* abs_coeff >= 1.0 && val < 2.0 */
+               exponent_bits = 7;
+               ls_bit_pos = 23;
+       } else {
+               /* abs_coeff >= 2.0 && val < 4.0 */
+               exponent_bits = 6;
+               ls_bit_pos = 24;
+       }
+
+       mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos,
CSC_MAX_VALS);
+       if (coeff < 0) {
+               sign_bit = 1;
+               mantissa = -mantissa;
+               mantissa &= ((1 << CSC_MAX_VALS) - 1);

I think there is a macro for this already ?

Thats for GAMMA_MAX, not for CSC_MAX. Or you mean the whole (1 <<
CSC_MAX_VALS -1) to be replaced with GET/SET bits ?
What I mean is - the above looks exactly like the GET_BIT_MASK (which
you introduced). Perhaps you can use it ?

Yes, Agree. but in later code review phase we realized that we dont even need this masking for mantissa. New patch set doesnt have this &ing, so we dont need this.
Regards,
Emil

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