On Thu, 08 Oct 2015, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote: >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: >> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> > >> > We accidentally lost the initial DPLL register write in >> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M >> > >> > The "three times for luck" hack probably saved us from a total >> > disaster. But anyway, bring the initial write back so that the >> > code actually makes some sense. >> > >> > Cc: stable@xxxxxxxxxxxxxxx >> > Cc: Nick Bowler <nbowler@xxxxxxxxxx> >> Reported-and-tested-by: Nick Bowler <nbowler@xxxxxxxxxx> >> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html >> >> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> > --- >> > drivers/gpu/drm/i915/intel_display.c | 2 ++ >> > 1 file changed, 2 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> > index 147e700..f4fdff9 100644 >> > --- a/drivers/gpu/drm/i915/intel_display.c >> > +++ b/drivers/gpu/drm/i915/intel_display.c >> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) >> > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); >> >> Don't we also need a POSTING_READ here to make sure the two-step 2x mode >> sequence is still followed? > > We don't do write combining on registers, and there are no shadow > register type of things to consider in this case either. > >> >> With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx> Daniel, are you happy with the responses about posting reads, for both patches? BR, Jani. >> > } >> > >> > + I915_WRITE(reg, dpll); >> > + >> > /* Wait for the clocks to stabilize. */ >> > POSTING_READ(reg); >> > udelay(150); >> > -- >> > 2.4.9 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Daniel Vetter >> Software Engineer, Intel Corporation >> http://blog.ffwll.ch > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
