Use init_l3_partitioning_workarounds() to set up the L3 partitioning
on context creation according to the hardware boot-up defaults for
each device.
Signed-off-by: Francisco Jerez <currojerez@xxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++++++++++++++++++++++++++++++--
1 file changed, 51 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e2e40d0..c4c39c4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -880,6 +880,36 @@ static int init_l3_partitioning_workarounds(struct intel_engine_cs *ring,
return 0;
}
+static int ivb_init_workarounds(struct intel_engine_cs *ring)
+{
+ /*
+ * Set up the default L3 partitioning of the hardware of 32
+ * ways (i.e. 256 KB on GT2 parts) for the URB and another 32
+ * ways for the RO partition.
+ */
+ return init_l3_partitioning_workarounds(ring, 32, 32, 0, 0);
+}
+
+static int vlv_init_workarounds(struct intel_engine_cs *ring)
+{
+ /*
+ * Set up the default L3 partitioning of the hardware of 64
+ * ways (i.e. 128 KB) for the URB, 16 ways (i.e. 32 KB) for
+ * the RO partition and another 16 ways for the DC.
+ */
+ return init_l3_partitioning_workarounds(ring, 64, 16, 16, 0);
+}
+
+static int hsw_init_workarounds(struct intel_engine_cs *ring)
+{
+ /*
+ * Set up the default L3 partitioning of the hardware of 32
+ * ways (i.e. 256 KB on GT2 parts) for the URB and another 32
+ * ways for the RO partition.
+ */
+ return init_l3_partitioning_workarounds(ring, 32, 32, 0, 0);
+}
+
static int gen8_init_workarounds(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
@@ -929,7 +959,12 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
GEN6_WIZ_HASHING_MASK,
GEN6_WIZ_HASHING_16x4);
- return 0;
+ /*
+ * Set up the default L3 partitioning of the hardware of 48
+ * ways (i.e. 384 KB on GT2 parts, 192 KB on GT1 parts and
+ * CHV) for the URB and another 48 ways for the RO partition.
+ */
+ return init_l3_partitioning_workarounds(ring, 48, 0, 0, 48);
}
static int bdw_init_workarounds(struct intel_engine_cs *ring)
@@ -1053,7 +1088,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
/* WaDisableSTUnitPowerOptimization:skl,bxt */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
- return 0;
+ /*
+ * Set up the default L3 partitioning of the hardware of 48
+ * ways (i.e. 384 KB on GT2 parts, 192 KB on GT1 parts and
+ * BXT) for the URB and another 48 ways for the RO partition.
+ */
+ return init_l3_partitioning_workarounds(ring, 48, 0, 0, 48);
}
static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
@@ -1175,6 +1215,15 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
dev_priv->workarounds.count = 0;
+ if (IS_IVYBRIDGE(dev))
+ return ivb_init_workarounds(ring);
+
+ if (IS_VALLEYVIEW(dev))
+ return vlv_init_workarounds(ring);
+
+ if (IS_HASWELL(dev))
+ return hsw_init_workarounds(ring);
+
if (IS_BROADWELL(dev))
return bdw_init_workarounds(ring);
--
2.5.1
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