For workarounds written in broadwell's init clock gating path,
use mmio workaround list.
Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 59 ++++++++++++++++++++++++-----------------
2 files changed, 38 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d41808a..a225d55 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3546,6 +3546,9 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
#define WA_CLR_BIT(t, addr, mask) \
WA_REG_##t(addr, mask, I915_READ((addr)) & ~(mask))
+#define WA_WRITE(t, addr, val) \
+ WA_REG_##t(addr, 0xffffffff, val)
+
static inline void intel_wa_init(struct i915_workarounds *w)
{
w->count = 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61136e1..7e01ef7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -62,9 +62,26 @@ void intel_wa_write_mmio(struct drm_i915_private *dev_priv,
assert_forcewakes_active(dev_priv);
- for (i = 0; i < w->count; i++)
+ for (i = 0; i < w->count; i++) {
+ u32 misccpctl;
+
+ /* WaTempDisableDOPClkGating:bdw */
+ const bool need_dop_clkgate =
+ w->reg[i].addr == GEN8_L3SQCREG1 &&
+ IS_BROADWELL(dev_priv->dev);
+
+ if (need_dop_clkgate) {
+ misccpctl = I915_READ(GEN7_MISCCPCTL);
+ I915_WRITE_FW(GEN7_MISCCPCTL,
+ misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ }
+
I915_WRITE_FW(w->reg[i].addr, w->reg[i].value);
+ if (need_dop_clkgate)
+ I915_WRITE_FW(GEN7_MISCCPCTL, misccpctl);
+ }
+
DRM_DEBUG_DRIVER("Number of Workarounds written: %d\n", w->count);
}
@@ -6514,10 +6531,14 @@ static void lpt_init_clock_gating(struct drm_device *dev)
* disabled when not needed anymore in order to save power.
*/
if (HAS_PCH_LPT_LP(dev))
- I915_WRITE(SOUTH_DSPCLK_GATE_D,
- I915_READ(SOUTH_DSPCLK_GATE_D) |
+ WA_SET_BIT(MMIO, SOUTH_DSPCLK_GATE_D,
PCH_LP_PARTITION_LEVEL_DISABLE);
+ /* XXX: This register is volatile with bdw. After
+ * reset you get weird values and after writing,
+ * the value you get is 0x00001000 so read/modify/write
+ * is dangerous
+ */
/* WADPOClockGatingDisable:hsw */
I915_WRITE(TRANS_CHICKEN1(PIPE_A),
I915_READ(TRANS_CHICKEN1(PIPE_A)) |
@@ -6540,52 +6561,42 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe;
- uint32_t misccpctl;
ilk_init_lp_watermarks(dev);
/* WaSwitchSolVfFArbitrationPriority:bdw */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+ WA_SET_BIT(MMIO, GAM_ECOCHK, HSW_ECOCHK_ARB_PRIO_SOL);
/* WaPsrDPAMaskVBlankInSRD:bdw */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
+ WA_SET_BIT(MMIO, CHICKEN_PAR1_1, DPA_MASK_VBLANK_SRD);
/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
for_each_pipe(dev_priv, pipe) {
- I915_WRITE(CHICKEN_PIPESL_1(pipe),
- I915_READ(CHICKEN_PIPESL_1(pipe)) |
+ WA_SET_BIT(MMIO, CHICKEN_PIPESL_1(pipe),
BDW_DPRS_MASK_VBLANK_SRD);
}
/* WaVSRefCountFullforceMissDisable:bdw */
/* WaDSRefCountFullforceMissDisable:bdw */
- I915_WRITE(GEN7_FF_THREAD_MODE,
- I915_READ(GEN7_FF_THREAD_MODE) &
- ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
+ WA_CLR_BIT(MMIO, GEN7_FF_THREAD_MODE,
+ GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME);
- I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+ WA_SET_BIT_MASKED(MMIO, GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
/* WaDisableSDEUnitClockGating:bdw */
- I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+ WA_SET_BIT(MMIO, GEN8_UCGCTL6,
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
- /*
- * WaProgramL3SqcReg1Default:bdw
- * WaTempDisableDOPClkGating:bdw
- */
- misccpctl = I915_READ(GEN7_MISCCPCTL);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
- I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+ /* WaProgramL3SqcReg1Default:bdw */
+ WA_WRITE(MMIO, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
/*
* WaGttCachingOffByDefault:bdw
* GTT cache may not work with big pages, so if those
* are ever enabled GTT cache may need to be disabled.
*/
- I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+ WA_WRITE(MMIO, HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
lpt_init_clock_gating(dev);
}
--
2.1.4
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