On 10/06/2015 12:05 PM, Jani Nikula wrote:
On Mon, 05 Oct 2015, Imre Deak <imre.deak@xxxxxxxxx> wrote:
On ma, 2015-10-05 at 20:52 +0530, Shobhit Kumar wrote:
Mostly reuse what is programmed by pre-os, but in case there is no
pre-os initialization, init the cdclk with the default value.
Cc: Imre Deak <imre.deak@xxxxxxxxx>
Signed-off-by: Shobhit Kumar <shobhit.kumar@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ddi.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2d3cc82..675c60d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2947,10 +2947,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
dev_priv->skl_boot_cdclk = cdclk_freq;
- if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
- DRM_ERROR("LCPLL1 is disabled\n");
- else
- intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+
+ skl_init_cdclk(dev_priv);
How does this prevent changing the clock if BIOS did enable some output?
We shouldn't change the clock in that case.
Random comment from the back, what about intentional cdclk change on
module load? We're supposed to have that for bdw [1] but last I checked
it failed... [2].
Yes. We will require cdclk change run time as well say if we hot plug a
DP 4k@60. So this capability is something that might really be needed.
Regards
Shobhit
BR,
Jani.
[1] http://mid.gmane.org/1433335514-4156-8-git-send-email-mika.kahola@xxxxxxxxx
[2] http://mid.gmane.org/87bngf4xk3.fsf@xxxxxxxxx
} else if (IS_BROXTON(dev)) {
broxton_init_cdclk(dev);
broxton_ddi_phy_init(dev);
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