On Tue, 06 Oct 2015, Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> wrote:
> From: Deepak S <deepak.s@xxxxxxxxx>
>
> v2: separate out device info into different GT (Damien)
> v3: Add is_kabylake to the KBL gt3 structuer (Damien)
> Sort the platforms in older -> newer order (Damien)
>
> Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> Signed-off-by: Deepak S <deepak.s@xxxxxxxxx>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 33 ++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> include/drm/i915_pciids.h | 29 +++++++++++++++++++++++++++++
> 3 files changed, 63 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1cb6b82..f42102d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -394,6 +394,34 @@ static const struct intel_device_info intel_broxton_info = {
> IVB_CURSOR_OFFSETS,
> };
>
> +static const struct intel_device_info intel_kabylake_info = {
> + .is_preliminary = 1,
> + .is_skylake = 1,
Now's the time to call the shots, is this really a good idea or not? See
VLV vs. CHV, we (okay, the royal we) still confuse ourselves with
IS_VALLEYVIEW.
Granted, 74 call sites for IS_SKYLAKE(), all of those would need to be
patched. We'd need something like "is skylake family" including SKL and
KBL. Some of them might be changed to be more like feature flags, which
is something we've decided we need to do more anyway.
BR,
Jani.
> + .is_kabylake = 1,
> + .gen = 9, .num_pipes = 3,
> + .need_gfx_hws = 1, .has_hotplug = 1,
> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> + .has_llc = 1,
> + .has_ddi = 1,
> + .has_fbc = 1,
> + GEN_DEFAULT_PIPEOFFSETS,
> + IVB_CURSOR_OFFSETS,
> +};
> +
> +static const struct intel_device_info intel_kabylake_gt3_info = {
> + .is_preliminary = 1,
> + .is_skylake = 1,
> + .is_kabylake = 1,
> + .gen = 9, .num_pipes = 3,
> + .need_gfx_hws = 1, .has_hotplug = 1,
> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> + .has_llc = 1,
> + .has_ddi = 1,
> + .has_fbc = 1,
> + GEN_DEFAULT_PIPEOFFSETS,
> + IVB_CURSOR_OFFSETS,
> +};
> +
> /*
> * Make sure any device matches here are from most specific to most
> * general. For example, since the Quanta match is based on the subsystem
> @@ -434,7 +462,10 @@ static const struct intel_device_info intel_broxton_info = {
> INTEL_SKL_GT1_IDS(&intel_skylake_info), \
> INTEL_SKL_GT2_IDS(&intel_skylake_info), \
> INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \
> - INTEL_BXT_IDS(&intel_broxton_info)
> + INTEL_BXT_IDS(&intel_broxton_info), \
> + INTEL_KBL_GT1_IDS(&intel_kabylake_info), \
> + INTEL_KBL_GT2_IDS(&intel_kabylake_info), \
> + INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info)
>
> static const struct pci_device_id pciidlist[] = { /* aka */
> INTEL_PCI_IDS,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 824e724..f7e9d7e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -765,6 +765,7 @@ struct intel_csr {
> func(is_valleyview) sep \
> func(is_haswell) sep \
> func(is_skylake) sep \
> + func(is_kabylake) sep \
> func(is_preliminary) sep \
> func(has_fbc) sep \
> func(has_pipe_cxsr) sep \
> @@ -2464,6 +2465,7 @@ struct drm_i915_cmd_table {
> #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
> #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
> #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
> +#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
> (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 17c4456..2e7a159 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -291,4 +291,33 @@
> INTEL_VGA_DEVICE(0x1A84, info), \
> INTEL_VGA_DEVICE(0x5A84, info)
>
> +#define INTEL_KBL_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> + INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> + INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> + INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> + INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> +
> +#define INTEL_KBL_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> + INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
> + INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
> + INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> +
> +#define INTEL_KBL_GT3_IDS(info) \
> + INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
> + INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
> +
> +#define INTEL_KBL_IDS(info) \
> + INTEL_KBL_GT1_IDS(info), \
> + INTEL_KBL_GT2_IDS(info), \
> + INTEL_KBL_GT3_IDS(info)
> +
> #endif /* _I915_PCIIDS_H */
> --
> 2.4.3
>
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--
Jani Nikula, Intel Open Source Technology Center
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