On Thu, Oct 01, 2015 at 07:59:27AM -0700, Kamble, Sagar A wrote:
> When using RC6 timeout mode, the timeout value
> should be written to GEN6_RC6_THRESHOLD.
>
> v2: Updated commit message. (Tom)
>
> v3: Rebase over whitespace differences. (Daniel)
>
> Cc: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
[TOR:] Still looks good.
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c98eee6..c16f496 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4791,7 +4791,6 @@ static void gen9_enable_rc6(struct drm_device *dev)
> I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
>
> I915_WRITE(GEN6_RC_SLEEP, 0);
> - I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>
> /* 2c: Program Coarse Power Gating Policies. */
> I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> @@ -4802,16 +4801,19 @@ static void gen9_enable_rc6(struct drm_device *dev)
> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> "on" : "off");
> -
> + /* WaRsUseTimeoutMode */
> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
> + I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
> I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> GEN7_RC_CTL_TO_MODE |
> rc6_mask);
> - else
> + } else {
> + I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> GEN6_RC_CTL_EI_MODE(1) |
> rc6_mask);
> + }
>
> /*
> * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> --
> 1.9.1
>
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