On Fri, Sep 18, 2015 at 04:38:27PM +0300, Jani Nikula wrote:
> On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@xxxxxxxxx> wrote:
> > DSP CLK_GATE registers are specific to BYT and CHT.
> > Avoid programming the same for BXT platform.
> >
> > v2: Rebased on latest drm nightly branch.
> >
> > v3: Fixed Jani's review comments
> >
> > Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
>
> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Merged everything in this series to dinq, with the exception of two
backlight-related patches which seem superseeded.
I'll expect follow-up work to clean up the encoder callback code
organization.
-Daniel
>
>
> > ---
> > drivers/gpu/drm/i915/intel_dsi.c | 8 +++++---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > index 6a0071f..08bade2 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -631,9 +631,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
> >
> > intel_dsi_clear_device_ready(encoder);
> >
> > - val = I915_READ(DSPCLK_GATE_D);
> > - val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> > - I915_WRITE(DSPCLK_GATE_D, val);
> > + if (!IS_BROXTON(dev_priv->dev)) {
> > + val = I915_READ(DSPCLK_GATE_D);
> > + val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> > + I915_WRITE(DSPCLK_GATE_D, val);
> > + }
> >
> > drm_panel_unprepare(intel_dsi->panel);
> >
> > --
> > 1.7.9.5
> >
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
