On Tue, Sep 29, 2015 at 07:32:51PM -0700, O'Rourke, Tom wrote:
> On Fri, Sep 25, 2015 at 11:46:56AM -0700, yu.dai@xxxxxxxxx wrote:
> > From: Alex Dai <yu.dai@xxxxxxxxx>
> >
> > GuC expects two bits for Render and Media domain separately when
> > driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
> > Render and bit 1 is for Media domain.
> >
> > v2: Keep sync with code for WaRsDoubleRc6WrlWithCoarsePowerGating
> >
> > v1: Add parameters definition to avoid magic value
> >
> > Signed-off-by: Alex Dai <yu.dai@xxxxxxxxx>
>
> Reviewed-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_guc_submission.c | 13 +++++++++++--
> > drivers/gpu/drm/i915/intel_guc_fwif.h | 3 +++
> > 2 files changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> > index 38b6ef4..036b42b 100644
> > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > @@ -155,12 +155,21 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
> > struct i915_guc_client *client)
> > {
> > struct drm_i915_private *dev_priv = guc_to_i915(guc);
> > + struct drm_device *dev = dev_priv->dev;
> > u32 data[2];
> >
> > data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> > - data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> > + /* WaRsDisableCoarsePowerGating:skl,bxt */
> > + if (!intel_enable_rc6(dev_priv->dev) ||
> > + (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> > + (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) ||
> > + (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> > + data[1] = 0;
> > + else
> > + /* bit 0 and 1 are for Render and Media domain separately */
> > + data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
> >
> > - return host2guc_action(guc, data, 2);
> > + return host2guc_action(guc, data, ARRAY_SIZE(data));
> > }
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > index 4029478..04ca777 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > @@ -296,6 +296,9 @@ struct guc_context_desc {
> > #define GUC_POWER_D2 3
> > #define GUC_POWER_D3 4
> >
> > +#define GUC_FORCEWAKE_RENDER (1 << 0)
> > +#define GUC_FORCEWAKE_MEDIA (1 << 1)
> > +
> > /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
> > enum host2guc_action {
> > HOST2GUC_ACTION_DEFAULT = 0x0,
> > --
> > 1.9.1
> >
> > _______________________________________________
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> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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