On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote:
> Dropping it as it is for pre-production stepping.
>
> Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 5 ++---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++------------
> 2 files changed, 13 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 256167b..e3baffd 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
> struct drm_device *dev = ring->dev;
> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>
> - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
> - (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
> wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
> wa_ctx_emit(batch, index,
Looks like we have some duplicated defines and whatnot. See
WaDisableMaskBasedCammingInRCC:skl,bxt in gen9_init_workarounds().
Maybe you can figure out why we have the same stuff in two places?
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 963b3ca..d5fdbc8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> GEN9_DG_MIRROR_FIX_ENABLE);
> }
>
> - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
> - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> - WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> - GEN9_RHWO_OPTIMIZATION_DISABLE);
> - /*
> - * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> - * but we do that in per ctx batchbuffer as there is an issue
> - * with this register not getting restored on ctx restore
> - */
> - }
> -
> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
> IS_BROXTON(dev)) {
> /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
> @@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> + if (INTEL_REVID(dev) < BXT_REVID_B0) {
> + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> + GEN9_RHWO_OPTIMIZATION_DISABLE);
> + /*
> + * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> + * but we do that in per ctx batchbuffer as there is an issue
> + * with this register not getting restored on ctx restore
> + */
> + }
> +
> return 0;
> }
>
> --
> 1.9.1
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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