On 9/25/2015 4:44 PM, Mika Kuoppala wrote:
Michel Thierry <michel.thierry@xxxxxxxxx> writes:
- ring->next_context_status_buffer = 0;
+
+ /*
+ * Instead of resetting the Context Status Buffer (CSB) read pointer to
+ * zero, we need to read the write pointer from hardware and use its
+ * value because "this register is power context save restored".
+ * Effectively, these states have been observed:
+ *
+ * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
+ * BDW | CSB regs not reset | CSB regs reset |
+ * CHT | CSB regs not reset | CSB regs not reset |
+ */
+ next_context_status_buffer_hw = I915_READ(RING_CONTEXT_STATUS_PTR(ring)) & 0x07;
+
+ /*
+ * When the CSB registers are reset (also after power-up / gpu reset),
+ * CSB write pointer is set to all 1's, which is not valid, use 0 in
+ * this special case.
+ */
+ if (next_context_status_buffer_hw == 0x7)
+ next_context_status_buffer_hw = 0;
If hardware has been reset and we have b111 here, I assume
the first write will be at index zero.
If we look at the interrupt code there is while (read_pointer <
write_pointer). Initializing next status buffer to zero
would mean that you miss the first write to csb[0].
If b111 is found, I think the correct value is 5.
Correct, it needs to be set to 5. Luckily, csb[0] would always be
Idle-to-Active, which we ignore.
-Mika
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