On Fri, Sep 25, 2015 at 02:23:34PM +0100, Arun Siluvery wrote: > Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++++++++++--------------- > 1 file changed, 10 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index c681c66..fdff606 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -819,6 +819,16 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring) > /* Wa4x4STCOptimizationDisable:bdw,chv */ > WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); > > + /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: > + * "The Hierarchical Z RAW Stall Optimization allows non-overlapping > + * polygons in the same 8x4 pixel/sample area to be processed without > + * stalling waiting for the earlier ones to write to Hierarchical Z > + * buffer." > + * > + * This optimization is off by default for BDW and CHV; turn it on. > + */ > + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > + Ok, so apart from the threadstall thing the rest looks reasonable. One request though, can you put w/as into some decent order? I suggest ordering based on the register, so eg. instpm mi_mode row chicken half slice chicken common slice chicken hdc chicken cache_mode_0 cache_mode_1 gt_mode I think that should match reasonably well what we have in most places. Or you can come up with something better if you wish, as long as the same/similar registers are grouped decently. > /* > * BSpec recommends 8x4 when MSAA is used, > * however in practice 16x4 seems fastest. > @@ -865,16 +875,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ > (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); > > - /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: > - * "The Hierarchical Z RAW Stall Optimization allows non-overlapping > - * polygons in the same 8x4 pixel/sample area to be processed without > - * stalling waiting for the earlier ones to write to Hierarchical Z > - * buffer." > - * > - * This optimization is off by default for Broadwell; turn it on. > - */ > - WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > - > return 0; > } > > @@ -898,11 +898,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) > HDC_FORCE_NON_COHERENT | > HDC_DONOT_FETCH_MEM_WHEN_MASKED); > > - /* According to the CACHE_MODE_0 default value documentation, some > - * CHV platforms disable this optimization by default. Turn it on. > - */ > - WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > - > /* Improve HiZ throughput on CHV. */ > WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
