On Fri, Sep 18, 2015 at 05:37:48PM +0100, Arun Siluvery wrote:
> On 17/09/2015 19:26, Dongwon Kim wrote:
> >We can calculate BXT values correctly from GFX fuse values without
> >hardcoding special limits.
> >
> >Cc: Imre Deak <imre.deak@xxxxxxxxx>
> >Cc: Matthew D Roper <matthew.d.roper@xxxxxxxxx>
> >signed-off-by: Dongwon Kim <dongwon.kim@xxxxxxxxx>
> >---
> > drivers/gpu/drm/i915/i915_dma.c | 11 -----------
> > 1 file changed, 11 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> >index 066a0ef..4fe82d7 100644
> >--- a/drivers/gpu/drm/i915/i915_dma.c
> >+++ b/drivers/gpu/drm/i915/i915_dma.c
> >@@ -631,17 +631,6 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> > u32 fuse2, s_enable, ss_disable, eu_disable;
> > u8 eu_mask = 0xff;
> >
> >- /*
> >- * BXT has a single slice. BXT also has at most 6 EU per subslice,
> >- * and therefore only the lowest 6 bits of the 8-bit EU disable
> >- * fields are valid.
> >- */
> >- if (IS_BROXTON(dev)) {
> >- s_max = 1;
> >- eu_max = 6;
> >- eu_mask = 0x3f;
> >- }
> >-
> > info = (struct intel_device_info *)&dev_priv->info;
> > fuse2 = I915_READ(GEN8_FUSE2);
> > s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
> >
>
> Without this change we are actually getting incorrect values in 'SSEU Device
> Info',
>
> # cat i915_sseu_status
> SSEU Device Info
> Available Slice Total: 1
> Available Subslice Total: 3
> Available Subslice Per Slice: 3
> Available EU Total: 15
> Available EU Per Subslice: 5
> Has Slice Power Gating: no
> Has Subslice Power Gating: yes
> Has EU Power Gating: yes
> SSEU Device Status
> Enabled Slice Total: 1
> Enabled Subslice Total: 3
> Enabled Subslice Per Slice: 3
> Enabled EU Total: 18
> Enabled EU Per Subslice: 6
>
> Looks good to me,
> Reviewed-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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