From: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
To reduce eDP T3 time check for digital port connected instead of
msleep. Maintain VBT time if HPD is not asserted on the port.
Current eDP T3 time is an msleep for the panel_power_up time specified
in VBT. The eDP specification allows maximum T3 time of 200ms.
Typically panels raise HPD from 70ms-105ms and are ready for AUX traffic
and training. Reading HPD will reduce power-on and resume times by over
100ms on systems with eDP HPD connected.
Signed-off-by: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 77e4115..7caf3ab 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -129,6 +129,8 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
+static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
+ struct intel_digital_port *port);
static unsigned int intel_dp_unused_lane_mask(int lane_count)
{
@@ -1772,6 +1774,7 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
u32 pp;
u32 pp_stat_reg, pp_ctrl_reg;
bool need_to_disable = !intel_dp->want_panel_vdd;
+ int i, step = 0;
lockdep_assert_held(&dev_priv->pps_mutex);
@@ -1809,7 +1812,15 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
if (!edp_have_panel_power(intel_dp)) {
DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
port_name(intel_dig_port->port));
- msleep(intel_dp->panel_power_up_delay);
+ step = intel_dp->panel_power_up_delay / 10;
+ for (i=0; i < intel_dp->panel_power_up_delay; i+=step) {
+ if (intel_digital_port_connected(dev_priv, intel_dig_port)) {
+ DRM_DEBUG_KMS("Port %c HPD detected\n",
+ port_name(intel_dig_port->port));
+ break;
+ }
+ msleep(10);
+ }
}
return need_to_disable;
--
1.7.9.5
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