Hello,
This change looks good but incomplete.
When changing RC6 from EI mode to TO mode,
should the time value in GEN6_RC6_THRESHOLD
be changed to hold the timeout value instead
of the evaluation interval period?
Should the workaround name be included in a comment?
While this workaround is unnamed for Broadwell, it is
called WaRsUseTimeoutMode for Skylake.
If possible, I would like to see those changes
squashed into this patch. If not, then putting
those changes in a followup patch would be OK.
Thanks,
Tom
On Mon, Sep 21, 2015 at 11:49:58AM -0700, Yu Dai wrote:
> Looks good to me.
> Reviewed-by: Alex Dai <yu.dai@xxxxxxxxx>
>
> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> >Enable TO mode for RC6 for SKL till D0 and BXT till A0.
> >
> >Cc: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
> >Cc: Akash Goel <akash.goel@xxxxxxxxx>
> >Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
> >---
> > drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
> > 1 file changed, 10 insertions(+), 3 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index c93d3a7..6e4818d 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -4847,9 +4847,16 @@ static void gen9_enable_rc6(struct drm_device *dev)
> > rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> > DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> > "on" : "off");
> >- I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> >- GEN6_RC_CTL_EI_MODE(1) |
> >- rc6_mask);
> >+
> >+ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
> >+ (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
> >+ I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> >+ GEN7_RC_CTL_TO_MODE |
> >+ rc6_mask);
> >+ else
> >+ I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> >+ GEN6_RC_CTL_EI_MODE(1) |
> >+ rc6_mask);
> > /*
> > * 3b: Enable Coarse Power Gating only when RC6 is enabled.
>
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