On Mon, Sep 14, 2015 at 03:19:56PM -0300, Paulo Zanoni wrote:
> Don't allow FBC for cases where the spec says we can't FBC.
>
> v2:
> - Just WARN_ON() the strides that should have been caught earlier
> (Daniel)
> - Make it a new function since I expect this to grow more.
> v3:
> - Document which IGT test is exercised by this.
> v4:
> - Implement the restrictions for gens 2-6 too (Ville).
> - Fix off-by-one mistake (Ville).
>
> Testcase: igt/kms_frontbuffer_tracking/fbc-badstride
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_fbc.c | 28 ++++++++++++++++++++++++++++
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3bf8a9b..8cf2969 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -948,6 +948,7 @@ struct i915_fbc {
> FBC_CHIP_DEFAULT, /* disabled by default on this chip */
> FBC_ROTATION, /* rotation is not supported */
> FBC_IN_DBG_MASTER, /* kernel debugger is active */
> + FBC_BAD_STRIDE, /* stride is not supported */
> } no_fbc_reason;
>
> bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 9e42079..db38091 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -480,6 +480,8 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason)
> return "rotation unsupported";
> case FBC_IN_DBG_MASTER:
> return "Kernel debugger is active";
> + case FBC_BAD_STRIDE:
> + return "framebuffer stride not supported";
> default:
> MISSING_CASE(reason);
> return "unknown reason";
> @@ -671,6 +673,27 @@ static int intel_fbc_setup_cfb(struct drm_i915_private *dev_priv, int size,
> return intel_fbc_alloc_cfb(dev_priv, size, fb_cpp);
> }
>
> +static bool stride_is_valid(struct drm_i915_private *dev_priv,
> + unsigned int stride)
> +{
> + /* These should have been caught earlier. */
> + WARN_ON(stride < 512);
> + WARN_ON((stride & (64 - 1)) != 0);
> +
> + /* Below are the additional FBC restrictions. */
> +
> + if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
> + return stride == 4096 || stride == 8192;
> +
> + if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
> + return false;
> +
> + if (stride > 16384)
> + return false;
Looks to match what I caught from my spec trawling trip last time.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> +
> + return true;
> +}
> +
> /**
> * __intel_fbc_update - enable/disable FBC as needed, unlocked
> * @dev_priv: i915 device instance
> @@ -781,6 +804,11 @@ static void __intel_fbc_update(struct drm_i915_private *dev_priv)
> goto out_disable;
> }
>
> + if (!stride_is_valid(dev_priv, fb->pitches[0])) {
> + set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE);
> + goto out_disable;
> + }
> +
> /* If the kernel debugger is active, always disable compression */
> if (in_dbg_master()) {
> set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER);
> --
> 2.5.1
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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