>-----Original Message-----
>From: Nikula, Jani
>Sent: Friday, September 18, 2015 6:58 PM
>To: Shankar, Uma; intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma
>Subject: Re: [BXT MIPI PATCH v3 07/14] drm/i915/bxt: Program Tx Rx and Dphy
>clocks
>
>On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@xxxxxxxxx> wrote:
>> From: Shashank Sharma <shashank.sharma@xxxxxxxxx>
>>
>> BXT DSI clocks are different than previous platforms. So adding a new
>> function to program following clocks and dividers:
>> 1. Program variable divider to generate input to Tx clock divider
>> (Output value must be < 39.5Mhz)
>> 2. Select divide by 2 option to get < 20Mhz for Tx clock 3. Program
>> 8by3 divider to generate Rx clock
>>
>> v2: Fixed Jani's review comments. Adjusted the Macro definition as
>> per convention. Simplified the logic for bit definitions for
>> MIPI PORT A and PORT C in same registers.
>>
>> v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
>> Jani's suggestion.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxxxx>
>> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
>
>Minor comments below, anyway
Thanks for the comments Jani. Will update while sending next patchset.
>Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 62
>++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_dsi_pll.c | 39 +++++++++++++++++++++
>> 2 files changed, 101 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 57c5dbf..e43b053 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7362,6 +7362,68 @@ enum skl_disp_power_wells {
>>
>> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
>C only */
>>
>> +/* BXT MIPI clock controls */
>> +#define BXT_MAX_VAR_OUTPUT_KHZ 39500
>> +
>> +#define BXT_MIPI_CLOCK_CTL 0x46090
>> +#define BXT_MIPI1_DIV_SHIFT 26
>> +#define BXT_MIPI2_DIV_SHIFT 10
>> +#define BXT_MIPI_DIV_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
>> + BXT_MIPI2_DIV_SHIFT)
>> +/* Var clock divider to generate TX source. Result must be < 39.5 M */
>> +#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
>> +#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
>> +#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
>> +
> BXT_MIPI2_ESCLK_VAR_DIV_MASK)
>> +
>> +#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
>> + (val << BXT_MIPI_DIV_SHIFT(port))
>> +/* TX control divider to select actual TX clock output from (8x/var) */
>> +#define BXT_MIPI1_TX_ESCLK_SHIFT 21
>> +#define BXT_MIPI2_TX_ESCLK_SHIFT 5
>> +#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
>> + BXT_MIPI2_TX_ESCLK_SHIFT)
>> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
>> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
>> +#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK,
>\
>> + (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> +#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
>> + (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
>> +/* BXT: Always prog DPHY dividers to 00 */
>
>Actually BXT A stepping W/A, but I don't know the name for it.
>> +#define BXT_MIPI1_DPHY_DIV_SHIFT 16
>> +#define BXT_MIPI2_DPHY_DIV_SHIFT 0
>> +#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
>> + _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
>> + BXT_MIPI2_DPHY_DIV_SHIFT)
>> +/* Program BXT Mipi clocks and dividers */ static void
>> +bxt_dsi_program_clocks(struct drm_device *dev, enum port port) {
>> + u32 tmp;
>> + u32 divider;
>> + u32 dsi_rate;
>> + u32 pll_ratio;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> + /* Get the current DSI rate(actual) */
>> + pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
>> + BXT_DSI_PLL_RATIO_MASK;
>> + dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
>> +
>> + /* Max possible output of clock is 39.5 MHz, program value -1 */
>> + divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
>> + tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
>> +
>> + /* Tx escape clock should be >=20MHz, so select divide by 2 */
>
>Actually the Tx escape clock must be as close as possible to, but not exceed, 20
>MHz.
>> + tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
>> +
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