On Tue, 01 Sep 2015, Uma Shankar <uma.shankar@xxxxxxxxx> wrote:
> From: Shashank Sharma <shashank.sharma@xxxxxxxxx>
>
> This patch contains changes to support DSI disble sequence in BXT.
> The changes are:
> 1. BXT specific changes in clear_device_ready function.
> 2. BXT specific changes in DSI disable and post-disable functions.
> 3. Add a new function to reset BXT Dphy clock and dividers
> (bxt_dsi_reset_clocks).
> 4. Moved some part of the vlv clock reset code, in a new function
> (vlv_dsi_reset_clocks) maintaining the exact same sequence.
> 5. Wrapper function to call corresponding reset clock function.
>
> v2: Fixed Jani's review comments.
>
> v3: Removed the GET_DSI_PORT_CTRL Macro for consistency with earlier
> implementations as per Jani's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 36 +++++++++++++++++--------------
> drivers/gpu/drm/i915/intel_dsi.h | 2 ++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 39 ++++++++++++++++++++++++++++++++++
> 3 files changed, 61 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 5a42f87..110a895 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -421,12 +421,15 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> u32 temp;
> + u32 port_ctrl;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> /* de-assert ip_tg_enable signal */
> - temp = I915_READ(MIPI_PORT_CTRL(port));
> - I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
> - POSTING_READ(MIPI_PORT_CTRL(port));
> + port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
> + MIPI_PORT_CTRL(port);
> + temp = I915_READ(port_ctrl);
> + I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
> + POSTING_READ(port_ctrl);
> }
> }
>
> @@ -550,12 +553,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
> /* Panel commands can be sent when clock is in LP11 */
> I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>
> - temp = I915_READ(MIPI_CTRL(port));
> - temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> - I915_WRITE(MIPI_CTRL(port), temp |
> - intel_dsi->escape_clk_div <<
> - ESCAPE_CLOCK_DIVIDER_SHIFT);
> -
> + intel_dsi_reset_clocks(encoder, port);
> I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>
> temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> @@ -574,10 +572,12 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>
> static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> {
> + struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> u32 val;
> + u32 port_ctrl = 0;
>
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> @@ -594,18 +594,22 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> ULPS_STATE_ENTER);
> usleep_range(2000, 2500);
>
> + if (IS_BROXTON(dev))
> + port_ctrl = BXT_MIPI_PORT_CTRL(port);
> + else if (IS_VALLEYVIEW(dev))
> + /* Common bit for both MIPI Port A & MIPI Port C */
> + port_ctrl = MIPI_PORT_CTRL(PORT_A);
> +
> /* Wait till Clock lanes are in LP-00 state for MIPI Port A
> * only. MIPI Port C has no similar bit for checking
> */
> - if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
> - == 0x00000), 30))
> + if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
> + == 0x00000), 30))
> DRM_ERROR("DSI LP not going Low\n");
>
> - /* Disable MIPI PHY transparent latch
> - * Common bit for both MIPI Port A & MIPI Port C
> - */
> - val = I915_READ(MIPI_PORT_CTRL(PORT_A));
> - I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
> + /* Disable MIPI PHY transparent latch */
> + val = I915_READ(port_ctrl);
> + I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
> usleep_range(1000, 1500);
>
> I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 759983e..078ea1b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -124,6 +124,8 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
> extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
> +extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
> + enum port port);
>
> struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 63f9aed..918bc5f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -389,6 +389,19 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
> return pclk;
> }
>
> +void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +{
> + u32 temp;
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +
> + temp = I915_READ(MIPI_CTRL(port));
> + temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> + I915_WRITE(MIPI_CTRL(port), temp |
> + intel_dsi->escape_clk_div <<
> + ESCAPE_CLOCK_DIVIDER_SHIFT);
> +}
> +
> /* Program BXT Mipi clocks and dividers */
> static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> {
> @@ -530,3 +543,29 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
> else if (IS_BROXTON(dev))
> bxt_disable_dsi_pll(encoder);
> }
> +
> +void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +{
> + u32 tmp;
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /* Clear old configurations */
> + tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> + tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> + I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +}
> +
> +void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> +{
> + struct drm_device *dev = encoder->base.dev;
> +
> + if (IS_BROXTON(dev))
> + bxt_dsi_reset_clocks(encoder, port);
> + else if (IS_VALLEYVIEW(dev))
> + vlv_dsi_reset_clocks(encoder, port);
> +}
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
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