From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
gen4/vlv/chv require DSPSURF to be 128k aligned. Try to respect that
in order to avoid ugly glitches.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
tools/intel_display_poller.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 99fd592..a6ae8d4 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -314,7 +314,7 @@ static void poll_pixel_flip(uint32_t devid, int pipe, int target_pixel, int targ
break;
}
- write_reg(surf, saved+4096);
+ write_reg(surf, saved+128*1024);
while (!quit){
pix2 = read_reg(pix) & PIPE_PIXEL_MASK;
@@ -763,7 +763,7 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
break;
}
- write_reg(surf, saved+4096);
+ write_reg(surf, saved+128*1024);
while (!quit) {
dsl2 = read_reg(dsl);
@@ -802,7 +802,7 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
saved = read_reg(surf);
surf1 = saved & ~0xfff;
- surf2 = surf1 + 4096;
+ surf2 = surf1 + 128*1024;
while (!quit) {
write_reg(surf, surf2);
--
2.4.6
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