On Tue, Sep 08, 2015 at 08:24:19AM +0100, Chris Wilson wrote: > In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit > reads. Due to the nature of the registers we try to read in this manner, > they may increment between the two instruction (e.g. a timestamp > counter). To keep the result accurate, we repeat the read if we detect > an overflow (i.e. the upper value varies). However, some harware is just > plain flaky and may endless loop as the the upper 32bits are not stable. > Just give up after a couple of tries and report whatever we read last. > > Reported-by: russianneuromancer@xxxxx > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906 > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Michał Winiarski <michal.winiarski@xxxxxxxxx> > Cc: Daniel Vetter <daniel.vetter@xxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 12870073d58f..8943dcb724a8 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); > #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) > > #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ > - u32 upper, lower, tmp; \ > + u32 upper, lower, tmp, loop = 0; \ > tmp = I915_READ(upper_reg); \ > do { \ > upper = tmp; \ > lower = I915_READ(lower_reg); \ > tmp = I915_READ(upper_reg); \ > - } while (upper != tmp); \ > + } while (upper != tmp && loop++ != 2); \ Maybe "loop++ < 2" for one more character of clarity. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
