On Wed, Aug 19, 2015 at 06:02:24PM -0700, Chandra Konduru wrote:
> This patch adds register definitions for skylake
> display NV12 support.
>
> Signed-off-by: Chandra Konduru <chandra.konduru@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1fa0554..c4d732f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5498,6 +5498,7 @@ enum skl_disp_power_wells {
> #define PS_SCALER_MODE_MASK (3 << 28)
> #define PS_SCALER_MODE_DYN (0 << 28)
> #define PS_SCALER_MODE_HQ (1 << 28)
> +#define PS_SCALER_MODE_NV12 (2 << 28)
> #define PS_PLANE_SEL_MASK (7 << 25)
> #define PS_PLANE_SEL(plane) ((plane + 1) << 25)
> #define PS_FILTER_MASK (3 << 23)
> @@ -5601,6 +5602,32 @@ enum skl_disp_power_wells {
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
>
> +
> +/*
> + * Skylake NV12 Register
> + */
> +#define PLANE_AUX_DIST_1_A 0x701c0
> +#define PLANE_AUX_DIST_2_A 0x702c0
> +#define PLANE_AUX_DIST_1_B 0x711c0
> +#define PLANE_AUX_DIST_2_B 0x712c0
> +#define _PLANE_AUX_DIST_1(pipe) \
> + _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
> +#define _PLANE_AUX_DIST_2(pipe) \
> + _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
> +#define PLANE_AUX_DIST(pipe, plane) \
> + _PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> +
> +#define PLANE_AUX_OFFSET_1_A 0x701c4
> +#define PLANE_AUX_OFFSET_2_A 0x702c4
> +#define PLANE_AUX_OFFSET_1_B 0x711c4
> +#define PLANE_AUX_OFFSET_2_B 0x712c4
> +#define _PLANE_AUX_OFFSET_1(pipe) \
> + _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> +#define _PLANE_AUX_OFFSET_2(pipe) \
> + _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> +#define PLANE_AUX_OFFSET(pipe, plane) \
> + _PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> +
Bspec seems entirely confused about these registers, not showing
AUX_OFFSET for SKL at all, and even the normal OFFSET has lost all the
information about the register offsets. But it does match what's there
for gen10, so I suppose it's all good.
But this stuff could be squashed to whichever patch(es) actually use the
new defines.
> /* legacy palette */
> #define _LGC_PALETTE_A 0x4a000
> #define _LGC_PALETTE_B 0x4a800
> --
> 1.7.9.5
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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