On Thu, Sep 03, 2015 at 04:40:13PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 03, 2015 at 04:24:35PM +0300, Imre Deak wrote:
> > This register exists only pre GEN5, but atm we also access it on
> > VLV/BXT/CHV. Prevent accessing it on these latter platforms.
>
> We don't have LVDS on any of those platforms.
Bah. Imre pointed out that we call intel_lvds_init() uncodnditionally on
all platforms, so the patch does make sense.
What a mess. Someone should really move the PPS unlock to some early
modeset init/resume code and also fix it for VLV/CHV/etc.
In the meantime this does what it says, so
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> >
> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_lvds.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> > index 0794dc8..a16308a 100644
> > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > @@ -955,7 +955,7 @@ void intel_lvds_init(struct drm_device *dev)
> > if (HAS_PCH_SPLIT(dev)) {
> > I915_WRITE(PCH_PP_CONTROL,
> > I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
> > - } else {
> > + } else if (INTEL_INFO(dev_priv)->gen < 5) {
> > I915_WRITE(PP_CONTROL,
> > I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
> > }
> > --
> > 2.1.4
>
> --
> Ville Syrjälä
> Intel OTC
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--
Ville Syrjälä
Intel OTC
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