Damien,
You reviewed v1 and then went on vacation for v2. Any chance you can
review v2?
Thanks,
Bob
On Tue, 21 Jul 2015 10:42:53 -0700
Bob Paauwe <bob.j.paauwe@xxxxxxxxx> wrote:
> Clearing the watermarks for all pipes/planes when updating the
> watermarks for a single CRTC change seems like the wrong thing to
> do here. As is, this code will ony update any pipe/plane watermarks
> that need updating and leave the remaining set to zero. Later, the
> watermark checks in check_wm_state() will flag these zero'd out pipe/plane
> watermarks and throw errors.
>
> By clearing only the watermark values associated with the specific crtc
> the other watermark values may remain unchanged.
>
> v2: Make sure all the dirty flags are cleared. Damien
> Clear all values assoicated with crtc/pipe being updated. Damien
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 26 +++++++++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a1d92b7..27c3126 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3670,6 +3670,26 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
> }
> }
>
> +static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
> +{
> + watermarks->wm_linetime[pipe] = 0;
> + memset(watermarks->plane[pipe], 0,
> + sizeof(uint32_t) * 8 * I915_MAX_PLANES);
> + memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
> + memset(watermarks->plane_trans[pipe],
> + 0, sizeof(uint32_t) * I915_MAX_PLANES);
> + watermarks->cursor_trans[pipe] = 0;
> +
> + /* Clear ddb entries for pipe */
> + memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
> + memset(&watermarks->ddb.plane[pipe], 0,
> + sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
> + memset(&watermarks->ddb.y_plane[pipe], 0,
> + sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
> + memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
> +
> +}
> +
> static void skl_update_wm(struct drm_crtc *crtc)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -3680,7 +3700,11 @@ static void skl_update_wm(struct drm_crtc *crtc)
> struct skl_pipe_wm pipe_wm = {};
> struct intel_wm_config config = {};
>
> - memset(results, 0, sizeof(*results));
> +
> + /* Clear all dirty flags */
> + memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
> +
> + skl_clear_wm(results, intel_crtc->pipe);
>
> skl_compute_wm_global_parameters(dev, &config);
>
--
--
Bob Paauwe
Bob.J.Paauwe@xxxxxxxxx
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
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