Hi, On 28 August 2015 at 16:55, Bob Paauwe <bob.j.paauwe@xxxxxxxxx> wrote: > On Fri, 28 Aug 2015 15:19:04 +0100 > Daniel Stone <daniel@xxxxxxxxxxxxx> wrote: >> For both this and the previous patch, cf. the corresponding patch for >> HSW/BDW[0], have you ensured these values are sanitised at startup, >> even if UEFI hasn't set something clever? Enabling fastboot on my >> (UEFI-based) BDW caused a black screen because were enabling CSC but >> with an empty table. >> >> Cheers, >> Daniel >> >> [0]: https://www.mail-archive.com/intel-gfx@xxxxxxxxxxxxxxxxxxxxx/msg67294.html > > Hmm, no I didn't. I assumed that it was all set up correctly since for > SKL+ the primary plane always has PIPE_CSC enabled. So does HSW/BDW. ;) The problem is that a CSC is only applied in the modeset path; when using 'fastboot' to skip the original modeset (i.e. to achieve flicker-free and quicker boot), the plane configuration applies CSC/gamma, but the tables are only applied on modeset. So you may end up with an invalid configuration (and blank screen), without a similar patch. > My two patches are > just to ensure that both the cursor and sprite planes also have it > enabled. If all the planes are configured the same, it causes a lot of > CRC failures in the igt tests. > > Unless I'm missing something (very possible), the pipe CSC setup/lack of > setup is a separate issue. Yeah, it is. But it'd be good to make sure Maarten's patch gets dragged in too. > Looking at Maarten's patch, it looks like mine above should have been > written as > > if (HAS_DDI(dev)) > > instead of all the separate conditions. Yeah, indeed. I'd misread the HAS_DDI bit myself, so it seems fine. Are you able to test Maarten's patch to always program the CSC tables and make sure it doesn't break SKL/BXT? Thanks, and sorry for the confusion. Cheers, Daniel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
