On Wednesday 12 August 2015 07:05 PM, Daniel Vetter wrote:
On Wed, Aug 12, 2015 at 03:23:48PM +0530, vikas.korjani@xxxxxxxxx wrote:From: vkorjani <vikas.korjani@xxxxxxxxx> This patch adds code to initialize Picture Parameter set (PPS) data structure for DSC. DSC is enabled than the bitrate should be calculated using the formula pixel_clock * bits_per_pixel / lane_count, where bits_per_pixel can be 8bpp, 10bpp, 12bpp. value of bits_per_pixel is available in step of 1/16 in pps date structure. DPHY parameters are computed based on data rate calculated as per bits_per_pixel provided in pps data structure. Signed-off-by: vkorjani <vikas.korjani@xxxxxxxxx> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_dsi.h | 5 +++++ drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 11 +++++++++++ drivers/gpu/drm/i915/intel_dsi_pll.c | 24 ++++++++++++++++-------- 3 files changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 24fc550..699f995 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -96,6 +96,11 @@ struct intel_dsi { u16 panel_on_delay; u16 panel_off_delay; u16 panel_pwr_cycle_delay; + + /*DSC Support */ + u8 dsc_enable; + struct vesa_dsc_pps_data pps_data; + u8 dsc_bpp; };struct intel_dsi_host {diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index a5e99ac..f893d37 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -413,6 +413,17 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) bits_per_pixel = 18; else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565) bits_per_pixel = 16; + else if (intel_dsi->pixel_format == VID_MODE_FORMAT_COMPRESSED && + dev_priv->vbt.dsc_param.dsc_support) { + intel_dsi->dsc_enable = true; + intel_dsi->dsc_bpp = + (intel_dsi->pps_data.bits_per_pixel / 16); + bits_per_pixel = intel_dsi->dsc_bpp; + intel_dsi->pps_data = + dev_priv->vbt.dsc_param.pps_data; + /*TODO If PPS not available in VBT compute PPS + * from capablity parameter set in vbt */We don't seem to feed back the dsi bits_per_pixel information into our computation of pipe_config->pipe_bpp. We probably need to fix that to actually be able to drive the higher bpc modes ... Wiring this up correctly should probably be a prep patch.
Yes will fix this.
Also do we have to compute bpp differently for dsc? Can't we just store bits_per_pixel somewhere? -Daniel
intel_dsi->dsc_bpp stores target bpp after compression. We can store orginal bpp in intel_dsi->dsi_bpp, some thing similar is done in this patch http://lists.freedesktop.org/archives/intel-gfx/2015-May/067627.html which is still under review.
+ }intel_dsi->operation_mode = mipi_config->is_cmd_mode;intel_dsi->video_mode_format = mipi_config->video_transfer_mode; diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index b647f13..38c9433 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -143,10 +143,17 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode, #else/* Get DSI clock from pixel clock */-static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) +static u32 dsi_clk_from_pclk(struct intel_encoder *encoder, + u32 pclk, int pixel_format, int lane_count) { + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 dsi_clk_khz; - u32 bpp = dsi_pixel_format_bpp(pixel_format); + u32 bpp; + + if (intel_dsi->dsc_enable) + bpp = intel_dsi->dsc_bpp; + else + bpp = dsi_pixel_format_bpp(pixel_format);/* DSI data rate = pixel clock * bits per pixel / lane countpixel clock is converted from KHz to Hz */ @@ -223,8 +230,8 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder) struct dsi_mnp dsi_mnp; u32 dsi_clk;- dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,- intel_dsi->lane_count); + dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk, + intel_dsi->pixel_format, intel_dsi->lane_count);ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk);if (ret) { @@ -410,8 +417,9 @@ u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; - /* pixel_format and pipe_bpp should agree */- assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); + /* pixel_format and pipe_bpp should agree if DSC is not enabled */ + if (!intel_dsi->dsc_enable) + assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); @@ -475,8 +483,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)u32 dsi_clk; u32 val;- dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,- intel_dsi->lane_count); + dsi_clk = dsi_clk_from_pclk(encoder, intel_dsi->pclk, + intel_dsi->pixel_format, intel_dsi->lane_count);/** From clock diagram, to get PLL ratio divider, divide double of DSI -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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