This patch sets default initial phase and trip to scale NV12 content. In future, if needed these can be set via properties or other means depending on incoming stream request. Until then defaults are fine. Signed-off-by: Chandra Konduru <chandra.konduru@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ drivers/gpu/drm/i915/intel_sprite.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 329651e..419660d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3098,6 +3098,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, int scaler_id = -1; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_state = to_intel_plane_state(plane->state); @@ -3181,6 +3182,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -3209,6 +3213,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index a1384a7..0ea9273 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -190,6 +190,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int scaler_id; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -264,6 +265,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? stride / 2 : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -292,6 +296,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane)); -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
