On Wed, Aug 19, 2015 at 07:51:57AM +0530, Deepak wrote:
>
>
> On 07/09/2015 02:15 AM, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > With DPIO powergating active the DPLL can't be accessed unless
> > something else is keeping the common lane in the channel on.
> > That means the PPS kick procedure could fail to enable the PLL.
> >
> > Power up some data lanes to force the common lane to power up
> > so that the PLL can be enabled temporarily.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 16 +++++++++++++---
> > 1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 8d088f3..817df87 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -341,7 +341,9 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > enum pipe pipe = intel_dp->pps_pipe;
> > - bool pll_enabled;
> > + bool pll_enabled, release_cl_override;
> > + enum dpio_phy phy = DPIO_PHY(pipe);
> > + enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> > uint32_t DP;
> >
> > if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
> > @@ -371,9 +373,13 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> > * The DPLL for the pipe must be enabled for this to work.
> > * So enable temporarily it if it's not already enabled.
> > */
> > - if (!pll_enabled)
> > + if (!pll_enabled) {
> > + release_cl_override = IS_CHERRYVIEW(dev) &&
> > + !chv_phy_powergate_ch(dev_priv, phy, ch, true);
> > +
> > vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
> > &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
> > + }
> >
> > /*
> > * Similar magic as in intel_dp_enable_port().
> > @@ -390,8 +396,12 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> > I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
> > POSTING_READ(intel_dp->output_reg);
> >
> > - if (!pll_enabled)
> > + if (!pll_enabled) {
> > vlv_force_pll_off(dev, pipe);
> > +
> > + if (release_cl_override)
> > + chv_phy_powergate_ch(dev_priv, phy, ch, false);
> > + }
> > }
> >
> > static enum pipe
> Change looks fine
> Reviewed-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
Note to Daniel: Please pick up v2 of this patch. The only change
was release_cl_override=false initialization to avoid a gcc warning.
--
Ville Syrjälä
Intel OTC
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