On Mon, Jun 16, 2014 at 04:11:00PM +0100, oscar.mateo@xxxxxxxxx wrote: > From: Oscar Mateo <oscar.mateo@xxxxxxxxx> > > Otherwise, we might receive a new interrupt before we have time to > ack the first one, eventually missing it. > > Without an atomic XCHG operation with mmio space, this patch merely > reduces the window in which we can miss an interrupt (especially when > you consider how heavyweight the I915_READ/I915_WRITE operations are). > > Notice that, before clearing a port-sourced interrupt in the IIR, the > corresponding interrupt source status in the PORT_HOTPLUG_STAT must be > cleared. > > Spotted by Bob Beckett <robert.beckett@xxxxxxxxx>. > > v2: > - Add warning to commit message and comments to the code as per Chris > Wilson's request. > - Imre Deak pointed out that the pipe underrun flag might not be signaled > in IIR, so do not make valleyview_pipestat_irq_handler depend on it. > > v3: Improve the source code comment. The code still talks about the necessity of clearing the PIPESTAT interrupt generators before resetting IIR, and since it is clearly doing so for the hpd interrupt, it probably should do so for the others. This patch introduces a regression in how we handle PIPESTAT on CHV (+VLV earlier). -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
