This is a v2 of [1]. Since v1 the HW team confirmed that there is an HW issue in A steppings with the GPU/CPU snoop logic, which explains why we need this workaround. In v2 I fixed a typo and limited the workaround to A steppings, since in later steppings this problem is fixed. [1] http://lists.freedesktop.org/archives/intel-gfx/2015-June/068218.html Imre Deak (2): drm/i915/bxt: work around HW coherency issue when accessing GPU seqno drm/i915/bxt: work around HW coherency issue for cached GEM mappings drivers/gpu/drm/i915/i915_gem.c | 11 ++++++++++- drivers/gpu/drm/i915/intel_lrc.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +++++++ 3 files changed, 37 insertions(+), 1 deletion(-) -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
