On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote:
> From: "Thulasimani,Sivakumar" <sivakumar.thulasimani@xxxxxxxxx>
>
> This reverts
> commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
> Author: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Date: Thu Mar 12 17:10:38 2015 +0200
>
> CHV does not support intermediate frequencies so reverting the
> patch that added it in the first place
My docs still say it does. Is there some undocumented problem with the
PLL or is this just a marketing decision?
>
> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 44f8a32..d9fb7a8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -95,9 +95,6 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> 324000, 432000, 540000 };
> static const int skl_rates[] = { 162000, 216000, 270000,
> 324000, 432000, 540000 };
> -static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> - 243000, 270000, 324000, 405000,
> - 420000, 432000, 540000 };
> static const int default_rates[] = { 162000, 270000, 540000 };
>
> /**
> @@ -1185,9 +1182,6 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
> } else if (IS_SKYLAKE(dev)) {
> *source_rates = skl_rates;
> return ARRAY_SIZE(skl_rates);
> - } else if (IS_CHERRYVIEW(dev)) {
> - *source_rates = chv_rates;
> - return ARRAY_SIZE(chv_rates);
> }
>
> *source_rates = default_rates;
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
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