From: vkorjani <vikas.korjani@xxxxxxxxx>
Program the PPS data from intel_dsc->vesa_dsc_pps_data
into display controller register DSCx_PICTURE_PARAMETER_SET_x.
DSC should be enabled in MIPI Port control register, after
programming PPS register
Disable DSC in disable sequence after disabling port.
Signed-off-by: vkorjani <vikas.korjani@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dsi.c | 197 +++++++++++++++++++++++++++++++++++++-
1 file changed, 196 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9963ec2..c011966 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -411,7 +411,12 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
/* de-assert ip_tg_enable signal */
port_ctrl = GET_DSI_PORT_CTRL(dev);
temp = I915_READ(port_ctrl);
- I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
+ temp &= ~DPI_ENABLE;
+ if (intel_dsi->dsc_enable) {
+ temp &= ~BXT_DSC_ENABLE;
+ temp &= ~RGB_FLIP_TO_BGR;
+ }
+ I915_WRITE(port_ctrl, temp);
POSTING_READ(port_ctrl);
}
}
@@ -876,6 +881,188 @@ static void set_dsi_timings(struct drm_encoder *encoder,
}
}
+static void intel_dsi_program_pps(struct drm_encoder *encoder, int port)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ u32 tmp = 0;
+
+ tmp |= intel_dsi->pps_data.dsc_ver_major << 0;
+ tmp |= intel_dsi->pps_data.dsc_ver_minor << 4;
+ tmp |= intel_dsi->pps_data.bit_per_comp << 8;
+ tmp |= intel_dsi->pps_data.line_buf_depth << 12;
+ tmp |= intel_dsi->pps_data.block_pred_enable << 16;
+ tmp |= intel_dsi->pps_data.convert_rgb << 17;
+ tmp |= intel_dsi->pps_data.enable_422 << 18;
+ tmp |= intel_dsi->pps_data.enable_vbr << 19;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_0(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.bits_per_pixel << 0;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_1(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.pic_height << 0;
+ tmp |= intel_dsi->pps_data.pic_width << 16;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_2(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.slice_height << 0;
+ tmp |= intel_dsi->pps_data.slice_width << 16;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_3(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.initial_xmit_delay << 0;
+ tmp |= intel_dsi->pps_data.initial_dec_delay << 16;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_4(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.scale_increment_interval << 0;
+ tmp |= intel_dsi->pps_data.scale_decrement_interval << 16;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_5(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.initial_scale_value << 0;
+ tmp |= intel_dsi->pps_data.first_line_bpg_offset << 8;
+ tmp |= intel_dsi->pps_data.flatness_min_qp << 16;
+ tmp |= intel_dsi->pps_data.flatness_max_qp << 24;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_6(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.slice_bpg_offset << 0;
+ tmp |= intel_dsi->pps_data.nfl_bpg_offset << 16;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_7(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.final_offset << 0;
+ tmp |= intel_dsi->pps_data.initial_offset << 16;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_8(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.rc_param.model_size << 0;
+ tmp |= intel_dsi->pps_data.rc_param.rc_edge_factor << 16;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_9(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.rc_param.rc_quant_incr_limit0 << 0;
+ tmp |= intel_dsi->pps_data.rc_param.rc_quant_incr_limit1 << 8;
+ tmp |= intel_dsi->pps_data.rc_param.rc_tgt_offset_hi << 16;
+ tmp |= intel_dsi->pps_data.rc_param.rc_tgt_offset_lo << 20;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_10(port), tmp);
+
+ tmp = 0;
+ tmp |= intel_dsi->pps_data.chunk_size << 0;
+ tmp |= 0x04 << 16;
+ tmp |= 0x78 << 20;
+ I915_WRITE(DSC_PICTURE_PARAMETER_SET_16(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[0] << 0 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[1] << 8 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[2] << 16|
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[3] << 24;
+ I915_WRITE(DSC_RC_BUF_THRESH_0_3(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[4] << 0 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[5] << 8 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[6] << 16 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[7] << 24;
+ I915_WRITE(DSC_RC_BUF_THRESH_4_7(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[8] << 0 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[9] << 8 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[10] << 16 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[11] << 24;
+ I915_WRITE(DSC_RC_BUF_THRESH_8_11(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_buf_thresh[12] << 0 |
+ intel_dsi->pps_data.rc_param.rc_buf_thresh[13] << 8;
+ I915_WRITE(DSC_RC_BUF_THRESH_12_13(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[0].range_min_qp|
+ intel_dsi->pps_data.rc_param.rc_range[0].range_max_qp << 5|
+ intel_dsi->pps_data.rc_param.rc_range[0].range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[1].range_min_qp << 16|
+ intel_dsi->pps_data.rc_param.rc_range[1].range_max_qp << 21|
+ intel_dsi->pps_data.rc_param.rc_range[1].
+ range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_0(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[2].range_min_qp|
+ intel_dsi->pps_data.rc_param.rc_range[2].range_max_qp << 5|
+ intel_dsi->pps_data.rc_param.rc_range[2].range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[3].range_min_qp << 16 |
+ intel_dsi->pps_data.rc_param.rc_range[3].range_max_qp << 21 |
+ intel_dsi->pps_data.rc_param.rc_range[3].range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_1(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[4].range_min_qp |
+ intel_dsi->pps_data.rc_param.rc_range[4].range_max_qp << 5 |
+ intel_dsi->pps_data.rc_param.rc_range[4].range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[5].range_min_qp << 16 |
+ intel_dsi->pps_data.rc_param.rc_range[5].range_max_qp << 21 |
+ intel_dsi->pps_data.rc_param.rc_range[5].range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_2(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[6].range_min_qp |
+ intel_dsi->pps_data.rc_param.rc_range[6].range_max_qp << 5 |
+ intel_dsi->pps_data.rc_param.rc_range[6].range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[7].range_min_qp << 16 |
+ intel_dsi->pps_data.rc_param.rc_range[7].range_max_qp << 21 |
+ intel_dsi->pps_data.rc_param.rc_range[7].range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_3(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[8].range_min_qp |
+ intel_dsi->pps_data.rc_param.rc_range[8].range_max_qp << 5 |
+ intel_dsi->pps_data.rc_param.rc_range[8].range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[9].range_min_qp << 16 |
+ intel_dsi->pps_data.rc_param.rc_range[9].range_max_qp << 21 |
+ intel_dsi->pps_data.rc_param.rc_range[9].range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_4(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[10].range_min_qp |
+ intel_dsi->pps_data.rc_param.rc_range[10].range_max_qp << 5 |
+ intel_dsi->pps_data.rc_param.rc_range[10].
+ range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[11].range_min_qp << 16 |
+ intel_dsi->pps_data.rc_param.rc_range[11].range_max_qp << 21 |
+ intel_dsi->pps_data.rc_param.rc_range[11].
+ range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_5(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[12].range_min_qp |
+ intel_dsi->pps_data.rc_param.rc_range[12].range_max_qp << 5 |
+ intel_dsi->pps_data.rc_param.rc_range[12].
+ range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[13].range_min_qp << 16 |
+ intel_dsi->pps_data.rc_param.rc_range[13].range_max_qp << 21 |
+ intel_dsi->pps_data.rc_param.rc_range[13].
+ range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_6(port), tmp);
+
+ tmp = 0;
+ tmp = intel_dsi->pps_data.rc_param.rc_range[14].range_min_qp |
+ intel_dsi->pps_data.rc_param.rc_range[14].range_max_qp << 5 |
+ intel_dsi->pps_data.rc_param.rc_range[14].
+ range_bpg_offset << 10|
+ intel_dsi->pps_data.rc_param.rc_range[15].range_min_qp << 16 |
+ intel_dsi->pps_data.rc_param.rc_range[15].range_max_qp << 21 |
+ intel_dsi->pps_data.rc_param.rc_range[15].
+ range_bpg_offset << 26;
+ I915_WRITE(DSC_RC_RANGE_PARAMETERS_7(port), tmp);
+}
+
static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
{
struct drm_encoder *encoder = &intel_encoder->base;
@@ -932,6 +1119,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
tmp &= ~BXT_PIPE_SELECT_MASK;
(port == PORT_C) ? (tmp |= BXT_PIPE_SELECT_C) :
(tmp |= BXT_PIPE_SELECT_A);
+
+ if (intel_dsi->dsc_enable) {
+ intel_dsi_program_pps(encoder, port);
+ /* Need to verify this delay */
+ msleep(20);
+ tmp |= BXT_DSC_ENABLE;
+ tmp |= RGB_FLIP_TO_BGR;
+ }
I915_WRITE(MIPI_CTRL(port), tmp);
}
--
1.7.9.5
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