On Thu, Aug 06, 2015 at 03:25:55PM +0100, Michel Thierry wrote: > On 8/6/2015 3:00 PM, Mika Kuoppala wrote: > >This register needs to be updated with masked writes. > > > >Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > >--- > > drivers/gpu/drm/i915/intel_lrc.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > >index 99bba8e..29347e7 100644 > >--- a/drivers/gpu/drm/i915/intel_lrc.c > >+++ b/drivers/gpu/drm/i915/intel_lrc.c > >@@ -521,7 +521,7 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring) > > ring->next_context_status_buffer = write_pointer % 6; > > > > I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), > >- ((u32)ring->next_context_status_buffer & 0x07) << 8); > >+ _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8)); > > } > > > > static int execlists_context_queue(struct drm_i915_gem_request *request) > >-- > >2.1.4 > > > > bspec agrees... but I remember seeing these bits being written without the > mask in gen8. Impact? Do I need this for -fixes with cc: stable? lrc is shipping as released code, please be a bit more elaborate in your commit messages. Thanks, Daniel > Reviewed-by: Michel Thierry <michel.thierry@xxxxxxxxx> > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
