On 8/4/2015 5:03 PM, Animesh Manna wrote:
On 8/4/2015 4:50 PM, Sunil Kamath wrote:
On Monday 03 August 2015 09:55 PM, Animesh Manna wrote:
As csr firmware is taking care of loading the firmware,
so no need for driver to load again.
Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx>
Cc: Damien Lespiau <damien.lespiau@xxxxxxxxx>
Cc: Imre Deak <imre.deak@xxxxxxxxx>
Cc: Sunil Kamath <sunil.kamath@xxxxxxxxx>
Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index e1d0102..02019e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1066,13 +1066,10 @@ static int bxt_resume_prepare(struct
drm_i915_private *dev_priv)
static int skl_resume_prepare(struct drm_i915_private *dev_priv)
{
- struct drm_device *dev = dev_priv->dev;
-
if (intel_csr_load_status_get(dev_priv) == FW_LOADED)
skl_disable_dc6(dev_priv);
skl_init_cdclk(dev_priv);
- intel_csr_load_program(dev);
Same comment as before.
The context save and restore program is reset on cold boot, warm
reset, PCI function level reset, and hibernate/suspend.
Need valid reason to do this change. If reading DC5/DC6 counters is a
concern, lets use this as just debug patch.
Dont hurry on this patch.
Need to close on the above opens.
- Sunil
Agree, I want to add this patch as part of this patch series, already
started communication with firmware team.
Waiting for suggestion, will followup and proceed further based on
suggestion.
Regards,
Animesh
Firmware team confirmed that one time firmware loading during driver loading is sufficient, no need
to load firmware in csr-address-space every suspend (dc6 entry) - resume (dc6 exit) flow, dmc will
take care of it.
- Animesh
return 0;
}
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