On Mon, Aug 03, 2015 at 09:55:35PM +0530, Animesh Manna wrote:
> Another interesting criteria to work dmc as expected is pw1 to be
> enabled by driver and dmc will shut it off in its execution
> sequence. If already disabled by driver dmc will get confuse and
> behave differently than expected found during pc10 entry issue
> for skl.
>
> So berfore we disable power-well 1, added check if dmc firmware is
> present and driver will not disable power well 1, but for any reason
> if firmware is not present of failed to load we can shut off the
> power well 1 which will save some power.
>
> As skl is currently fully dependent on dmc to go in lowest possible
> power state (dc6) but the same is not applicable for bxt. Display
> engine can enter into dc9 without dmc, hence unblocking disable call.
>
> v1: Initial version.
>
> v2: Based on revire commnents from Sunil,
> - condition check for pw1 is moved in skl_set_power_well.
There's another patch from Damien/Paulo to do some similar fumbling
between LCPLL and PW1. We probably want to completely take away PW1 from
being controlled by the power wells code and push it all into the rpm code
(where we either disable pw1, pw-misc and lcpll in one go or leave it all
to the dmc firmware).
-Daniel
>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx>
> Cc: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Sunil Kamath <sunil.kamath@xxxxxxxxx>
> Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index c660245..00cd4ff 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -636,9 +636,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> }
> } else {
> if (enable_requested) {
> - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> - POSTING_READ(HSW_PWR_WELL_DRIVER);
> - DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> + if (IS_SKYLAKE(dev) &&
> + (power_well->data == SKL_DISP_PW_1) &&
> + (intel_csr_load_status_get(dev_priv) == FW_LOADED))
> + DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
> + else {
> + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
> + POSTING_READ(HSW_PWR_WELL_DRIVER);
> + DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
> + }
>
> if (GEN9_ENABLE_DC5(dev) &&
> power_well->data == SKL_DISP_PW_2)
> --
> 2.0.2
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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