On Tue, Aug 04, 2015 at 11:21:53AM +0100, Arun Siluvery wrote:
> This WA is implemented in init_context as well as WA batch init.
> There are also some dependent bits need to be set in other registers
> for this to be complete.
>
> v2: behaviour of disable gather at set shader bit can be specified by
> two different registers, use a better option (Ben).
>
> Cc: Ben Widawsky <benjamin.widawsky@xxxxxxxxx>
> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++++++++++++++
> 3 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8991cd5..8719a5a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1721,6 +1721,10 @@ enum skl_disp_power_wells {
> #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
> #define FW_BLC 0x020d8
> #define FW_BLC2 0x020dc
> +#define GEN7_RS_CHICKEN 0x20DC
> +#define GEN9_RS_CHICKEN_DISABLE_GATHER_AT_SHADER (1<<2)
> +#define GEN7_FF_SLICE_CHICKEN1 0x20E0
> +#define GEN9_PER_CTX_DISABLE_GATHER_CONTROL (1<<15)
> #define FW_BLC_SELF 0x020e0 /* 915+ only */
> #define FW_BLC_SELF_EN_MASK (1<<31)
> #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
> @@ -5836,6 +5840,7 @@ enum skl_disp_power_wells {
> # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
> # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
> #define COMMON_SLICE_CHICKEN2 0x7014
> +#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12)
> # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
>
> #define HIZ_CHICKEN 0x7018
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 9faad82..d3a03f3 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1292,6 +1292,14 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
> struct drm_device *dev = ring->dev;
> uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>
> + /* WA to reset "disable gather at set shader slice" bit */
> + if (IS_SKYLAKE(dev)) {
> + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> + wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2);
> + wa_ctx_emit(batch, index,
> + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE));
> + }
> +
The workaround is confusing because it says "SKL+, but explicitly excludes the
next GEN, which leads me to believe it either shouldn't be SKL+ (it should be
SKL), or we need it for BXT. We can always add it later if needed. Also, several
of the ancillary bits do refer to BXT.
(Also, still confused why you don't do a revid check here, but if you do what I
request below, we can ignore that).
> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
> (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index dcd1b8f..5e8e5f9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -985,6 +985,17 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
>
> + /* WA to gather at set shader - skl,bxt
> + * These are dependent bits need to be set for the WA.
> + */
> + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) > SKL_REVID_D0) ||
> + (IS_BROXTON(dev) && INTEL_REVID(dev) > BXT_REVID_A0)) {
> + WA_SET_BIT_MASKED(GEN7_FF_SLICE_CHICKEN1,
> + GEN9_PER_CTX_DISABLE_GATHER_CONTROL);
> + WA_SET_BIT_MASKED(GEN7_RS_CHICKEN,
> + GEN9_RS_CHICKEN_DISABLE_GATHER_AT_SHADER);
> + }
> +
This is a very poorly documented workaround... Reading this again, I believe
this doesn't follow the text from the documentation and this hunk does the wrong
thing. The text clearly states we must clear bit 12 of CS_COMMON2 to workaround
the issue (before each context restore, but it shouldn't hurt to do it
initially).
"If this field is set, Disable at Set Shader Common Slice in register 0x20DC bit
2 must also be set."
To clear this up even further, I think the reason these two registers are talked
about is that the CS, or RS need to match the behavior for the common slice.
Since the default is to always use the BTP for the streamers, and we're
explicitly forcing the CS_COMMON to do the gather at BTP parsing, this has no
meaning.
As we're explicitly clearing the field, I don't think we should be doing
anything with RS_CHICKEN (20dc) or CS_DEBUG_MODE2 (20d8).
I tested on my platform with the hunk removed, and it seems to make no
difference. (Interestingly, I learned that the patch before this is at least as
important as this one). I did not test BXT.
So unless you can justify keeping this hunk, I'd like it gone, and the defines
removed. Sorry for the churn. With that changed, I am happy with no REVID check
too, so:
Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx>
Tested-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> return 0;
> }
>
> @@ -1068,6 +1079,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
> HDC_FENCE_DEST_SLM_DISABLE |
> HDC_BARRIER_PERFORMANCE_DISABLE);
>
> + /* WA to Disable gather at set shader - skl
> + * This bit needs to be reset in Per ctx WA batch and it is also
> + * dependent on other bits in different register, all of them need
> + * be set for the WA to be complete.
> + */
> + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN9_DISABLE_GATHER_SET_SHADER_SLICE);
> +
> return skl_tune_iz_hashing(ring);
> }
>
--
Ben Widawsky, Intel Open Source Technology Center
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