Em Ter, 2015-08-04 às 17:01 +0530, Sunil Kamath escreveu: > On Tuesday 04 August 2015 12:17 AM, Zanoni, Paulo R wrote: > > Em Seg, 2015-08-03 às 21:55 +0530, Animesh Manna escreveu: > > > The following patches helps to solve PC10 entry issue for SKL. > > > Detailed description about the changes done to solve the issue > > > is mentioned in commit message of each patch. > > > > > > All these patches are send earlier for review as part of > > > "Redesign of > > > dmc firmware loading" patch series. Now skl specific bug-fixes > > > are > > > seperated out and sending as seperate patch series to make it > > > simple. > > Hello > > > > I find interesting that even with this series, igt/pm_rpm/rte > > fails. We > > don't seem to be doing runtime PM, yet we allow PC10 somehow. Maybe > > it > > would be nice to have some kind of documentation explaining what's > > different on SKL and how things are supposed to work. > > Why do you say that rpm is not done for SKL? > Even in SKL its runtime PM that triggers DC6 enable then PKGC10. > > Vathsala, Rajneesh, > please add your comments and observations here. Every single RPM IGT test case fails on current -nightly, even with these patches applied. We just don't ever runtime suspend on SKL. OTOH I already submitted "[PATCH 3/4] drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences", which makes SKL actually runtime suspend, so most of the tests start passing - although we still have some failures. OTOH, since you claim we actually reach PC10 without [patch 3/4], then maybe we don't need RPM at all? Still, we'd need IGT tests for that. > > - Sunil > > > > > Also, since this feature is not relying on runtime PM, it would be > > really nice to elaborate some IGT tests for it. You could even try > > to > > automate PC10 entry checks by reading the appropriate MSR regsiters > > - > > just like we do with PC8 on HSW. > > > > Thanks, > > Paulo > > > > > Animesh Manna (5): > > > drm/i915/gen9: Removed byte swapping for csr firmware > > > drm/i915/skl: Making DC6 entry is the last call in suspend > > > flow. > > > drm/i915/skl: Do not disable cdclk PLL if csr firmware is > > > present. > > > drm/i915/skl: Block disable call for pw1 if dmc firmware is > > > present. > > > drm/i915/skl: Removed csr firmware load in resume path. > > > > > > drivers/gpu/drm/i915/i915_drv.c | 13 +++++----- > > > drivers/gpu/drm/i915/i915_drv.h | 2 +- > > > drivers/gpu/drm/i915/intel_csr.c | 16 +++--------- > > > drivers/gpu/drm/i915/intel_display.c | 11 +++++--- > > > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 45 +++++++++++++----- > > > ----- > > > ---------- > > > 6 files changed, 37 insertions(+), 52 deletions(-) > > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
