Re: [PATCH v2 1/4] drm/i915: Enable WA batch buffers for Gen9

["Siluvery, Arun" <arun.siluvery@xxxxxxxxxxxxxxx>]

On 10/07/2015 16:52, Mika Kuoppala wrote:
> Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx> writes:
>
> > This patch only enables support for Gen9, the actual WA will be
> > initialized in subsequent patches.
> >
> > The WARN that we use to warn user if WA batch support is not available
> > for a particular Gen is replaced with DRM_ERROR as warning here doesn't
> > really add much value.
> >
> > v2: include all infrastructure bits in this patch so that subsequent
> > changes only correspond the WA added (Chris)
> >
> > Cc: Imre Deak <imre.deak@xxxxxxxxx>
> > Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
>
> The wa_ctx_emits need index as second param now. With those,
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
Thanks Mika, I will send the updated patches.
Your r-b tag is for all patches correct?
Should I include the tag while sending the patches?

regards
Arun

> > ---
> >   drivers/gpu/drm/i915/intel_lrc.c | 50 +++++++++++++++++++++++++++++++++++++---
> >   1 file changed, 47 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index 23ff018..1e88b3b 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1269,6 +1269,35 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
> >   	return wa_ctx_end(wa_ctx, *offset = index, 1);
> >   }
> >
> > +static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
> > +				    struct i915_wa_ctx_bb *wa_ctx,
> > +				    uint32_t *const batch,
> > +				    uint32_t *offset)
> > +{
> > +	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
> > +
> > +	/* FIXME: Replace me with WA */
> > +	wa_ctx_emit(batch, MI_NOOP);
> > +
> > +	/* Pad to end of cacheline */
> > +	while (index % CACHELINE_DWORDS)
> > +		wa_ctx_emit(batch, MI_NOOP);
> > +
> > +	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
> > +}
> > +
> > +static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
> > +			       struct i915_wa_ctx_bb *wa_ctx,
> > +			       uint32_t *const batch,
> > +			       uint32_t *offset)
> > +{
> > +	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
> > +
> > +	wa_ctx_emit(batch, MI_BATCH_BUFFER_END);
> > +
> > +	return wa_ctx_end(wa_ctx, *offset = index, 1);
> > +}
> > +
> >   static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
> >   {
> >   	int ret;
> > @@ -1310,10 +1339,11 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring)
> >   	WARN_ON(ring->id != RCS);
> >
> >   	/* update this when WA for higher Gen are added */
> > -	if (WARN(INTEL_INFO(ring->dev)->gen > 8,
> > -		 "WA batch buffer is not initialized for Gen%d\n",
> > -		 INTEL_INFO(ring->dev)->gen))
> > +	if (INTEL_INFO(ring->dev)->gen > 9) {
> > +		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
> > +			  INTEL_INFO(ring->dev)->gen);
> >   		return 0;
> > +	}
> >
> >   	/* some WA perform writes to scratch page, ensure it is valid */
> >   	if (ring->scratch.obj == NULL) {
> > @@ -1345,6 +1375,20 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring)
> >   					  &offset);
> >   		if (ret)
> >   			goto out;
> > +	} else if (INTEL_INFO(ring->dev)->gen == 9) {
> > +		ret = gen9_init_indirectctx_bb(ring,
> > +					       &wa_ctx->indirect_ctx,
> > +					       batch,
> > +					       &offset);
> > +		if (ret)
> > +			goto out;
> > +
> > +		ret = gen9_init_perctx_bb(ring,
> > +					  &wa_ctx->per_ctx,
> > +					  batch,
> > +					  &offset);
> > +		if (ret)
> > +			goto out;
> >   	}
> >
> >   out:
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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