On ma, 2015-07-06 at 14:44 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Since > commit e62925567c7926e78bc8ca976cde5c28ea265a49 > Author: Vandana Kannan <vandana.kannan@xxxxxxxxx> > Date: Wed Jul 1 17:02:57 2015 +0530 > > drm/i915/bxt: BUNs related to port PLL > > BXT DPLL can now generate frequencies in the 216-223 MHz range. > Adjust the HDMI port clock checks to account for the reduced range > of invalid frequencies. > > Cc: Vandana Kannan <vandana.kannan@xxxxxxxxx> > Cc: Imre Deak <imre.deak@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Ville wrote a tool for CHV that calculates the valid frequencies based on the algorithm in the kernel. With the help of that I verified that this matches the list of target frequencies bxt_find_best_dpll() will accept, so: Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_hdmi.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index c7e912b..70bad5b 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1174,9 +1174,12 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, > if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) > return MODE_CLOCK_HIGH; > > - /* CHV/BXT DPLL can't generate 216-240 MHz */ > - if ((IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) && > - clock > 216000 && clock < 240000) > + /* BXT DPLL can't generate 223-240 MHz */ > + if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) > + return MODE_CLOCK_RANGE; > + > + /* CHV DPLL can't generate 216-240 MHz */ > + if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) > return MODE_CLOCK_RANGE; > > return MODE_OK; _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
