On Wed, Jul 08, 2015 at 05:51:22PM +0300, Francisco Jerez wrote:
Just a few style nits, didn't look at the actual contents...
<snip>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a29bcc..9b17260 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7906,4 +7906,13 @@ enum skl_disp_power_wells {
> #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
> #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
>
> +/* MOCS (Memory Object Control State) registers */
> +#define GEN9_LNCFCMOCS0 (0xB020) /* L3 Cache Control base */
> +
> +#define GEN9_GFX_MOCS_0 (0xc800) /* Graphics MOCS base register*/
> +#define GEN9_MFX0_MOCS_0 (0xc900) /* Media 0 MOCS base register*/
> +#define GEN9_MFX1_MOCS_0 (0xcA00) /* Media 1 MOCS base register*/
> +#define GEN9_VEBOX_MOCS_0 (0xcB00) /* Video MOCS base register*/
> +#define GEN9_BLT_MOCS_0 (0xcc00) /* Blitter MOCS base register*/
No need for all the parens.
<snip>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index e0299fb..64f89f99 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -42,6 +42,7 @@ int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
> void intel_logical_ring_stop(struct intel_engine_cs *ring);
> void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
> int intel_logical_rings_init(struct drm_device *dev);
> +int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
>
> int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
> /**
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> new file mode 100644
> index 0000000..130bcbe
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -0,0 +1,337 @@
> +/*
> + * Copyright (c) 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions: *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + */
> +
> +#include "intel_mocs.h"
> +#include "intel_lrc.h"
> +#include "intel_ringbuffer.h"
> +
> +/* structures required */
> +struct drm_i915_mocs_entry {
> + u32 control_value;
> + u16 l3cc_value;
> +};
> +
> +struct drm_i915_mocs_table {
> + u32 size;
> + const struct drm_i915_mocs_entry *table;
> +};
> +
> +/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> +#define LE_CACHEABILITY(value) (value << 0)
> +#define LE_TGT_CACHE(value) (value << 2)
> +#define LE_LRUM(value) (value << 4)
> +#define LE_AOM(value) (value << 6)
> +#define LE_RSC(value) (value << 7)
> +#define LE_SCC(value) (value << 8)
> +#define LE_PFM(value) (value << 11)
> +#define LE_SCF(value) (value << 14)
> +
> +/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
> +#define L3_ESC(value) (value << 0)
> +#define L3_SCC(value) (value << 1)
> +#define L3_CACHEABILITY(value) (value << 4)
These should have parens arond (value) to avoid suprises if someone
passes in something more complicated than a single number.
> +
> +/* Helper defines */
> +#define GEN9_NUM_MOCS_ENTRIES (62) /* 62 out of 64 - 63 & 64 are reserved. */
> +
> +/* (e)LLC caching options */
> +#define LE_PAGETABLE (0)
> +#define LE_UC (1)
> +#define LE_WT (2)
> +#define LE_WB (3)
> +
> +/* L3 caching options */
> +#define L3_DIRECT (0)
> +#define L3_UC (1)
> +#define L3_RESERVED (2)
> +#define L3_WB (3)
> +
> +/* Target cache */
> +#define ELLC (0)
> +#define LLC (1)
> +#define LLC_ELLC (2)
And these parens seem useless.
--
Ville Syrjälä
Intel OTC
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