On Thu, Jul 02, 2015 at 04:33:42PM +0300, Ville Syrjälä wrote: > On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote: > > Ville noticed that the PLL HW readout code parsed the fractional > > divider value as if the fractional divider was always enabled. This may > > result in a port clock state check mismatch if the preceeding modeset > > disabled the fractional divider, but left a non-zero divider value in > > the register. > > > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Queued for -fixes (with cc: stable), thanks for the patch. -Daniel > > > --- > > drivers/gpu/drm/i915/intel_display.c | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 5cc405d..2b7ebf1 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -8021,7 +8021,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, > > int pipe = pipe_config->cpu_transcoder; > > enum dpio_channel port = vlv_pipe_to_channel(pipe); > > intel_clock_t clock; > > - u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; > > + u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; > > int refclk = 100000; > > > > mutex_lock(&dev_priv->sb_lock); > > @@ -8029,10 +8029,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, > > pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); > > pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); > > pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); > > + pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); > > mutex_unlock(&dev_priv->sb_lock); > > > > clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; > > - clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); > > + clock.m2 = (pll_dw0 & 0xff) << 22; > > + if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) > > + clock.m2 |= pll_dw2 & 0x3fffff; > > clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; > > clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; > > clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; > > -- > > 2.1.4 > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
