For dual link panel scenarios there are new fileds added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.
Signed-off-by: Deepak M <m.deepak@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_bios.c | 13 +++++++++++++
drivers/gpu/drm/i915/intel_bios.h | 5 ++++-
drivers/gpu/drm/i915/intel_dsi.h | 2 ++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 6d8f0d4..fe4c9ed 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -789,6 +789,19 @@ parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
return;
}
+ /*
+ * These below bits will inform us on which port the panel blk_cntrl and
+ * CABC ON/OFF commands needs to be sent in case of dual link panels
+ * u16 dl_cabc_port:2;
+ * u16 pwm_bkl_ctrl:2;
+ * But these are introduced from the VBT version 197 onwards, so making
+ * sure that these bits are zero in the pervious versions.
+ */
+ if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+ dev_priv->vbt.dsi.config->dl_cabc_port = 0;
+ dev_priv->vbt.dsi.config->pwm_bkl_ctrl = 0;
+ }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index af0b476..492be9c 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -820,7 +820,10 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
- u16 rsvd3:9;
+ u16 rgb_flip:1;
+ u16 dl_cabc_port:2;
+ u16 pwm_bkl_ctrl:2;
+ u16 rsvd3:4;
u16 rsvd4;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2784ac4..c39e39d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -71,6 +71,8 @@ struct intel_dsi {
u8 escape_clk_div;
u8 dual_link;
+ u8 dl_cabc_port;
+ u8 pwm_blk_ctrl;
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
--
1.7.9.5
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