Just like the DC5/DC6 states on SKL, but this time for BXT's DC9. Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 878cc7f..0bc8b37 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2626,6 +2626,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) mutex_lock(&csr->lock); seq_printf(m, "DC5 allowed: %s\n", yesno(csr->dc5_allowed)); seq_printf(m, "DC6 allowed: %s\n", yesno(csr->dc6_allowed)); + seq_printf(m, "DC9 allowed: %s\n", yesno(csr->dc9_allowed)); mutex_unlock(&csr->lock); if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 99a09dd..129e148 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -751,7 +751,7 @@ struct intel_csr { uint32_t mmioaddr[8]; uint32_t mmiodata[8]; enum csr_state state; - bool dc5_allowed, dc6_allowed; + bool dc5_allowed, dc6_allowed, dc9_allowed; }; #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index bfcc990..31f003a4 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -415,6 +415,7 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) void bxt_enable_dc9(struct drm_i915_private *dev_priv) { + struct intel_csr *csr = &dev_priv->csr; uint32_t val; assert_can_enable_dc9(dev_priv); @@ -425,10 +426,15 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv) val |= DC_STATE_EN_DC9; I915_WRITE(DC_STATE_EN, val); POSTING_READ(DC_STATE_EN); + + mutex_lock(&csr->lock); + csr->dc9_allowed = true; + mutex_unlock(&csr->lock); } void bxt_disable_dc9(struct drm_i915_private *dev_priv) { + struct intel_csr *csr = &dev_priv->csr; uint32_t val; assert_can_disable_dc9(dev_priv); @@ -439,6 +445,10 @@ void bxt_disable_dc9(struct drm_i915_private *dev_priv) val &= ~DC_STATE_EN_DC9; I915_WRITE(DC_STATE_EN, val); POSTING_READ(DC_STATE_EN); + + mutex_lock(&csr->lock); + csr->dc9_allowed = false; + mutex_unlock(&csr->lock); } static void gen9_set_dc_state_debugmask_memory_up( -- 2.1.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx