Nick Hoath <nicholas.hoath@xxxxxxxxx> writes: > On 29/06/2015 15:08, Mika Kuoppala wrote: >> >> Hi, >> >> Nick Hoath <nicholas.hoath@xxxxxxxxx> writes: >> >>> From: Rafael Barbalho <rafael.barbalho@xxxxxxxxx> >>> >>> Signed-off-by: Rafael Barbalho <rafael.barbalho@xxxxxxxxx> >>> Signed-off-by: Nick Hoath <nicholas.hoath@xxxxxxxxx> >>> --- >>> drivers/gpu/drm/i915/intel_pm.c | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >>> index 32ff034..d635d0a 100644 >>> --- a/drivers/gpu/drm/i915/intel_pm.c >>> +++ b/drivers/gpu/drm/i915/intel_pm.c >>> @@ -59,6 +59,11 @@ static void gen9_init_clock_gating(struct drm_device *dev) >>> /* WaEnableLbsSlaRetryTimerDecrement:skl */ >>> I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | >>> GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); >>> + >>> + /* WaVSRefCountFullforceMissDisable:skl,bxt */ >>> + I915_WRITE(GEN7_FF_THREAD_MODE, >>> + I915_READ(GEN7_FF_THREAD_MODE) & >>> + ~(GEN7_FF_VS_REF_CNT_FFME)); >>> } >>> >> >> This bit 19 seems to be about Tesselation DOP gating disable >> with gen9+ onwards. And with that workaroundname, the applicability >> should be hsw,bdw. I am confused. >> > > The specs say these WAs are required for GEN9+, BDW & HSW. So I'm > at a loss to see the confusion. > I was wrong about the bit 19. It is bit 15. But the issue remains, bit 15 is not about VS reference counts but TDS bypassing on SKL. The meaning of bitsfield have changed on skl. So we need to hunt down where the refcount disable has been moved? -Mika >> -Mika >> >> >>> static void skl_init_clock_gating(struct drm_device *dev) >>> -- >>> 2.1.1 >>> >>> _______________________________________________ >>> Intel-gfx mailing list >>> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
