+static struct drm_i915_mocs_entry broxton_mocs_table[] = {
+ /* {0x00000001, 0x0010} */
+ {(MOCS_CACHEABILITY(EDRAM_UC) | MOCS_TGT_CACHE(ELLC) |
+ MOCS_LRUM(0) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_UC))},
+ /* {0x00000005, 0x0010} */
+ {(MOCS_CACHEABILITY(EDRAM_UC) | MOCS_TGT_CACHE(LLC) |
+ MOCS_LRUM(0) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_UC))},
+ /* {0x00000005, 0x0030} */
+ {(MOCS_CACHEABILITY(EDRAM_UC) | MOCS_TGT_CACHE(LLC) |
+ MOCS_LRUM(0) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_WB))},
+ /* {0x00000017, 0x0030} */
+ {(MOCS_CACHEABILITY(EDRAM_WB) | MOCS_TGT_CACHE(LLC) |
+ MOCS_LRUM(1) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_WB))},
+ /* {0x00000017, 0x0010} */
+ {(MOCS_CACHEABILITY(EDRAM_WB) | MOCS_TGT_CACHE(LLC) |
+ MOCS_LRUM(1) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_UC))},
+ /* {0x00000019, 0x0010} */
+ {(MOCS_CACHEABILITY(EDRAM_UC) | MOCS_TGT_CACHE(LLC_ELLC) |
+ MOCS_LRUM(1) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_UC))},
+ /* {0x00000037, 0x0030} */
+ {(MOCS_CACHEABILITY(EDRAM_WB) | MOCS_TGT_CACHE(LLC) |
+ MOCS_LRUM(3) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_WB))},
+ /* {0x00000037, 0x0010} */
+ {(MOCS_CACHEABILITY(EDRAM_WB) | MOCS_TGT_CACHE(LLC) |
+ MOCS_LRUM(3) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_UC))},
+ /* {0x0000003b, 0x0010} */
+ {(MOCS_CACHEABILITY(EDRAM_WB) | MOCS_TGT_CACHE(LLC_ELLC) |
+ MOCS_LRUM(3) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
+ MOC_PFM(0) | MOCS_SCF(0)),
+ (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_UC))},
+};
+
+/**
+ * get_mocs_settings
+ *
+ * This function will return the values of the MOCS table that needs to
+ * be programmed for the platform. It will return the values that need
+ * to be programmed and if they need to be programmed.
+ *
+ * If the return values is false then the registers do not need programming.
+ */
+static bool get_mocs_settings(struct drm_device *dev,
+ struct drm_i915_mocs_table *table) {
+ bool result = false;
+
+ if (IS_SKYLAKE(dev)) {
+ table->size = ARRAY_SIZE(skylake_mocs_table);
+ table->table = skylake_mocs_table;
+ result = true;
+ } else if (IS_BROXTON(dev)) {
+ table->size = ARRAY_SIZE(broxton_mocs_table);
+ table->table = broxton_mocs_table;
+ result = true;
+ } else {
+ /* Platform that should have a MOCS table does not */
+ WARN_ON(INTEL_INFO(dev)->gen >= 9);
+ }
+
+ return result;
+}
+
+/**
+ * emit_mocs_control_table() - emit the mocs control table
+ * @ringbuf: DRM device.
+ * @table: The values to program into the control regs.
+ * @reg_base: The base for the Engine that needs to be programmed.
+ *
+ * This function simply emits a MI_LOAD_REGISTER_IMM command for the
+ * given table starting at the given address.
+ *
+ * Return: Nothing.
+ */
+static void emit_mocs_control_table(struct intel_ringbuffer *ringbuf,
+ struct drm_i915_mocs_table *table,
+ u32 reg_base)
+{
+ unsigned int index;
+
+ intel_logical_ring_emit(ringbuf,
+ MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
+
+ for (index = 0; index < table->size; index++) {
+ intel_logical_ring_emit(ringbuf, reg_base + (index * 4));
+ intel_logical_ring_emit(ringbuf,
+ table->table[index].control_value);
+ }
+
+ /*
+ * Ok, now set the unused entries to uncached. These entries are
+ * officially undefined and no contact is given for the contents and
+ * settings is given for these entries.
+ *
+ * Entry 0 in the table is uncached - so we are just written that
+ * value to all the used entries.
+ */
+ for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
+ intel_logical_ring_emit(ringbuf, reg_base + (index * 4));
+ intel_logical_ring_emit(ringbuf, table->table[0].control_value);
+ }
+
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+}
+
+/**
+ * emit_mocs_l3cc_table() - emit the mocs control table
+ * @ringbuf: DRM device.
+ * @table: The values to program into the control regs.
+ *
+ * This function simply emits a MI_LOAD_REGISTER_IMM command for the
+ * given table starting at the given address. This register set is programmed
+ * in pairs.
+ *
+ * Return: Nothing.
+ */
+static void emit_mocs_l3cc_table(struct intel_ringbuffer *ringbuf,
+ struct drm_i915_mocs_table *table) {
+ unsigned int count;
+ unsigned int i;
+ u32 value;
+ u32 filler = (table->table[0].l3cc_value & 0xffff) |
+ ((table->table[0].l3cc_value & 0xffff) << 16);
+
+ intel_logical_ring_emit(ringbuf,
+ MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
+
+ for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
+ value = (table->table[count].l3cc_value & 0xffff) |
+ ((table->table[count + 1].l3cc_value & 0xffff) << 16);
+
+ intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + (i * 4));
+ intel_logical_ring_emit(ringbuf, value);
+ }
+
+ if (table->size & 0x01) {
+ /* Odd table size - 1 left over */
+ value = (table->table[count].l3cc_value & 0xffff) |
+ ((table->table[0].l3cc_value & 0xffff) << 16);
+ } else
+ value = filler;
+
+ /*
+ * Now set the rest of the table to uncached - use entry 0 as this
+ * will be uncached. Leave the last pair as initialised as they are
+ * reserved by the hardware.
+ */
+ for (; i < (GEN9_NUM_MOCS_ENTRIES / 2) - 1; i++) {
+ intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + (i * 4));
+ intel_logical_ring_emit(ringbuf, value);
+
+ value = filler;
+ }
+
+ intel_logical_ring_emit(ringbuf, MI_NOOP);
+}
+
+/*
+ * gen9_program_mocs() - program the MOCS register.
+ *
+ * ring: The ring that the programming batch will be run in.
+ * ctx: The intel_context to be used.
+ *
+ * This function will emit a batch buffer with the values required for
+ * programming the MOCS register values for all the currently supported
+ * rings.
+ *
+ * These registers are partially stored in the RCS context, so they are
+ * emitted at the same time so that when a context is created these registers
+ * are set up. These registers have to be emitted into the start of the
+ * context as setting the ELSP will re-init some of these registers back
+ * to the hw values.
+ *
+ * Return: 0 on success, otherwise the error status.
+ */
+int gen9_program_mocs(struct intel_engine_cs *ring,
+ struct intel_context *ctx)
+{
+ int ret = 0;
+
+ struct drm_i915_mocs_table t;
+ struct drm_device *dev = ring->dev;
+ struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
+
+ if (get_mocs_settings(dev, &t)) {
+ u32 table_size;
+
+ /*
+ * OK. For each supported ring:
+ * number of mocs entries * 2 dwords for each control_value
+ * plus number of mocs entries /2 dwords for l3cc values.
+ *
+ * Plus 1 for the load command and 1 for the NOOP per ring
+ * and the l3cc programming.
+ */
+ table_size = GEN9_NUM_MOCS_RINGS *
+ ((2 * GEN9_NUM_MOCS_ENTRIES) + 2) +
+ GEN9_NUM_MOCS_ENTRIES + 2;
+ ret = intel_logical_ring_begin(ringbuf, ctx, table_size);
+ if (ret) {
+ DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
+ return ret;
+ }
+
+ /* program the control registers */
+ emit_mocs_control_table(ringbuf, &t, GEN9_GFX_MOCS_0);
+ emit_mocs_control_table(ringbuf, &t, GEN9_MFX0_MOCS_0);
+ emit_mocs_control_table(ringbuf, &t, GEN9_MFX1_MOCS_0);
+ emit_mocs_control_table(ringbuf, &t, GEN9_VEBOX_MOCS_0);
+ emit_mocs_control_table(ringbuf, &t, GEN9_BLT_MOCS_0);
+
+ /* now program the l3cc registers */
+ emit_mocs_l3cc_table(ringbuf, &t);
+
+ intel_logical_ring_advance(ringbuf);
+
+ DRM_DEBUG("MOCS: Table set in Context\n");
+ } else {
+ DRM_DEBUG("MOCS: Table Not supported on platform\n");
+ }
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/intel_mocs.h b/drivers/gpu/drm/i915/intel_mocs.h
new file mode 100644
index 0000000..e2780ce
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_mocs.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Peter Antoine <peter.antoine@xxxxxxxxx>
+ */
+
+#ifndef INTEL_MOCS_H
+#define INTEL_MOCS_H
+
+/**
+ * DOC: Memory Objects Control State (MOCS)
+ *
+ * Motivation:
+ * In previous Gens the MOCS settings was a value that was set by user land as
+ * part of the batch. In Gen9 this has changed to be a single table (per ring)
+ * that all batches now reference by index instead of programming the MOCS
+ * directly.
+ *
+ * The one wrinkle in this is that only PART of the MOCS tables are included
+ * in context (The GFX_MOCS_0 - GFX_MOCS_64 and the LNCFCMOCS0 - LNCFCMOCS32
+ * registers). The rest are not (the settings for the other rings).
+ *
+ * This table needs to be set at system start-up because the way the table
+ * interacts with the contexts and the GmmLib interface.
+ *
+ *
+ * Implementation:
+ *
+ * The table is programmed on a platform basis from a table that is generated
+ * from the one that has been agreed by the different responsible parties. This
+ * tables (one per supported platform) is defined in intel_mocs.c and is
+ * programmed in the first batch after the context is loaded (with the hardware
+ * workarounds). This will then let the usual context handling keep the MOCS in
+ * step.
+ */
+
+#include <drm/drmP.h>
+#include "i915_drv.h"
+
+int gen9_program_mocs(struct intel_engine_cs *ring,
+ struct intel_context *ctx);
+
+#endif
+
