On Fri, Jun 26, 2015 at 02:18:39PM -0300, Paulo Zanoni wrote: > > @@ -1311,13 +1320,15 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */, > > unsigned int p = dividers[d].list[i]; > > uint64_t dco_freq = p * afe_clock; > > > > - skl_wrpll_try_divider(&ctx, > > - dco_central_freq[dco], > > - dco_freq, > > - p); > > + if (skl_wrpll_try_divider(&ctx, > > + dco_central_freq[dco], > > + dco_freq, > > + p)) > > + goto skip_remaining_dividers; > > Bikeshed: instead of touching skl_wrpll_try_divider(), you could just: > > if (ctx.min_deviation == 0) goto skip_remaining_dividers; > > That would keep the logic of the optimization restricted to this > function. IMHO, much simpler. > > With or without changes: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> I like that, v2 it is! -- Damien _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
