Content based DRRS support is implemented in
eDP DRRS module also.
Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_drv.h | 3 +++
drivers/gpu/drm/i915/intel_edp_drrs.c | 29 +++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b364a68..3a5cff8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -419,6 +419,9 @@ struct intel_crtc_state {
/* m2_n2 for eDP downclock */
struct intel_link_m_n dp_m2_n2;
+
+ /* m3_n3 for eDP Media playback DRRS */
+ struct intel_link_m_n dp_m3_n3;
bool has_drrs;
/*
diff --git a/drivers/gpu/drm/i915/intel_edp_drrs.c b/drivers/gpu/drm/i915/intel_edp_drrs.c
index 8968e4c..173c281 100644
--- a/drivers/gpu/drm/i915/intel_edp_drrs.c
+++ b/drivers/gpu/drm/i915/intel_edp_drrs.c
@@ -45,6 +45,8 @@ static int vlv_edp_set_drrs_state(struct intel_encoder *encoder,
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct i915_drrs *drrs;
u32 reg, val;
if (!crtc)
@@ -53,6 +55,10 @@ static int vlv_edp_set_drrs_state(struct intel_encoder *encoder,
reg = PIPECONF(crtc->config->cpu_transcoder);
val = I915_READ(reg);
+ drrs = dev_priv->drrs[get_drrs_struct_index_for_crtc(dev_priv, crtc)];
+ if (!drrs || !drrs->has_drrs)
+ return -EINVAL;
+
switch (target_rr_type) {
case DRRS_HIGH_RR:
if (IS_VALLEYVIEW(dev))
@@ -62,6 +68,29 @@ static int vlv_edp_set_drrs_state(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev))
val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
break;
+ case DRRS_MEDIA_RR:
+ if (drrs->connector->panel.target_mode->vrefresh ==
+ drrs->connector->panel.fixed_mode->vrefresh) {
+ /* Exiting from MEDIA_RR */
+ if (IS_VALLEYVIEW(dev))
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+
+ intel_dp_set_m_n(crtc, &crtc->config->dp_m_n,
+ &crtc->config->dp_m2_n2);
+ } else {
+ intel_link_compute_m_n(crtc->config->pipe_bpp,
+ intel_dp->lane_count,
+ drrs->connector->panel.target_mode->clock,
+ crtc->config->port_clock,
+ &crtc->config->dp_m3_n3);
+
+ if (IS_VALLEYVIEW(dev))
+ val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+
+ intel_dp_set_m_n(crtc, &crtc->config->dp_m_n,
+ &crtc->config->dp_m3_n3);
+ }
+ break;
default:
DRM_ERROR("invalid refresh rate type\n");
return -EINVAL;
--
1.7.9.5
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